gpio: Add gpio_mmio32 driver to access basic 32-bit i/o registers
It is envisaged that this will be used by SoC or board code to make
available fixed purpose memory-mapped i/o registers to the rest of the
system which normally expects to use GPIO devices, e.g. for driving chip
select lines, LEDs or reading button states.
As such, the driver code doesn't provide a kconfig based configuration
mechanism, instead SoC/board code can hard-wire the devices it wants
with something simple like:
GPIO_MMIO32_INIT(misc_reg1, "MISC1", 0x12345678, 0xffffffffu)
Then, for example, if bit N of the register at 0x12345678 is wired up as
an SPI device chip select line, the SPI driver could be configured to
use pin N of the "MISC1" GPIO driver and not need any other board
specific code.
Change-Id: Ib02fcbab73fcf9637e25834db060fb3108626f47
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2016-12-21 00:55:41 +08:00
|
|
|
/*
|
|
|
|
|
* Copyright (c) 2016 Linaro Ltd.
|
|
|
|
|
*
|
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef _GPIO_MMIO32_H_
|
|
|
|
|
#define _GPIO_MMIO32_H_
|
|
|
|
|
|
|
|
|
|
#include <device.h>
|
|
|
|
|
#include <gpio.h>
|
Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-19 23:32:08 +08:00
|
|
|
#include <zephyr/types.h>
|
gpio: Add gpio_mmio32 driver to access basic 32-bit i/o registers
It is envisaged that this will be used by SoC or board code to make
available fixed purpose memory-mapped i/o registers to the rest of the
system which normally expects to use GPIO devices, e.g. for driving chip
select lines, LEDs or reading button states.
As such, the driver code doesn't provide a kconfig based configuration
mechanism, instead SoC/board code can hard-wire the devices it wants
with something simple like:
GPIO_MMIO32_INIT(misc_reg1, "MISC1", 0x12345678, 0xffffffffu)
Then, for example, if bit N of the register at 0x12345678 is wired up as
an SPI device chip select line, the SPI driver could be configured to
use pin N of the "MISC1" GPIO driver and not need any other board
specific code.
Change-Id: Ib02fcbab73fcf9637e25834db060fb3108626f47
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2016-12-21 00:55:41 +08:00
|
|
|
|
|
|
|
|
struct gpio_mmio32_config {
|
2017-04-21 23:55:34 +08:00
|
|
|
volatile u32_t *reg;
|
|
|
|
|
u32_t mask;
|
gpio: Add gpio_mmio32 driver to access basic 32-bit i/o registers
It is envisaged that this will be used by SoC or board code to make
available fixed purpose memory-mapped i/o registers to the rest of the
system which normally expects to use GPIO devices, e.g. for driving chip
select lines, LEDs or reading button states.
As such, the driver code doesn't provide a kconfig based configuration
mechanism, instead SoC/board code can hard-wire the devices it wants
with something simple like:
GPIO_MMIO32_INIT(misc_reg1, "MISC1", 0x12345678, 0xffffffffu)
Then, for example, if bit N of the register at 0x12345678 is wired up as
an SPI device chip select line, the SPI driver could be configured to
use pin N of the "MISC1" GPIO driver and not need any other board
specific code.
Change-Id: Ib02fcbab73fcf9637e25834db060fb3108626f47
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2016-12-21 00:55:41 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct gpio_mmio32_context {
|
|
|
|
|
const struct gpio_mmio32_config *config;
|
2017-04-21 23:55:34 +08:00
|
|
|
u32_t invert; /* Mask of 'reg' bits that should be inverted */
|
gpio: Add gpio_mmio32 driver to access basic 32-bit i/o registers
It is envisaged that this will be used by SoC or board code to make
available fixed purpose memory-mapped i/o registers to the rest of the
system which normally expects to use GPIO devices, e.g. for driving chip
select lines, LEDs or reading button states.
As such, the driver code doesn't provide a kconfig based configuration
mechanism, instead SoC/board code can hard-wire the devices it wants
with something simple like:
GPIO_MMIO32_INIT(misc_reg1, "MISC1", 0x12345678, 0xffffffffu)
Then, for example, if bit N of the register at 0x12345678 is wired up as
an SPI device chip select line, the SPI driver could be configured to
use pin N of the "MISC1" GPIO driver and not need any other board
specific code.
Change-Id: Ib02fcbab73fcf9637e25834db060fb3108626f47
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2016-12-21 00:55:41 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int gpio_mmio32_init(struct device *dev);
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_GPIO_MMIO32
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Create a device object for accessing a simple 32-bit i/o register using the
|
|
|
|
|
* same APIs as GPIO drivers.
|
|
|
|
|
*
|
|
|
|
|
* @param _dev_name Device name.
|
|
|
|
|
* @param _drv_name The name this instance of the driver exposes to the system.
|
|
|
|
|
* @param _address The address of the 32-bit i/o register the device will
|
|
|
|
|
* provide access to.
|
|
|
|
|
* @param _mask Mask of bits in the register that it is valid to access.
|
|
|
|
|
* E.g. 0xffffffffu to allow access to all of them.
|
|
|
|
|
*
|
|
|
|
|
* @see DEVICE_INIT
|
|
|
|
|
*/
|
|
|
|
|
#define GPIO_MMIO32_INIT(_dev_name, _drv_name, _address, _mask) \
|
|
|
|
|
\
|
|
|
|
|
static struct gpio_mmio32_context _dev_name##_dev_data; \
|
|
|
|
|
\
|
|
|
|
|
static const struct gpio_mmio32_config _dev_name##_dev_cfg = { \
|
2017-04-21 23:55:34 +08:00
|
|
|
.reg = (volatile u32_t *)_address, \
|
gpio: Add gpio_mmio32 driver to access basic 32-bit i/o registers
It is envisaged that this will be used by SoC or board code to make
available fixed purpose memory-mapped i/o registers to the rest of the
system which normally expects to use GPIO devices, e.g. for driving chip
select lines, LEDs or reading button states.
As such, the driver code doesn't provide a kconfig based configuration
mechanism, instead SoC/board code can hard-wire the devices it wants
with something simple like:
GPIO_MMIO32_INIT(misc_reg1, "MISC1", 0x12345678, 0xffffffffu)
Then, for example, if bit N of the register at 0x12345678 is wired up as
an SPI device chip select line, the SPI driver could be configured to
use pin N of the "MISC1" GPIO driver and not need any other board
specific code.
Change-Id: Ib02fcbab73fcf9637e25834db060fb3108626f47
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2016-12-21 00:55:41 +08:00
|
|
|
.mask = _mask, \
|
|
|
|
|
}; \
|
|
|
|
|
\
|
|
|
|
|
DEVICE_INIT(_dev_name, _drv_name, \
|
|
|
|
|
&gpio_mmio32_init, \
|
|
|
|
|
&_dev_name##_dev_data, \
|
|
|
|
|
&_dev_name##_dev_cfg, \
|
|
|
|
|
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE)
|
|
|
|
|
|
|
|
|
|
#else /* CONFIG_GPIO_MMIO32 */
|
|
|
|
|
|
|
|
|
|
/* Null definition for when support not configured into kernel */
|
|
|
|
|
#define GPIO_MMIO32_INIT(_dev_name, _drv_name, _address, _mask)
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#endif /* _GPIO_MMIO32_H_ */
|
