2015-04-11 07:44:37 +08:00
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/* cpu.h - automatically selects the correct arch.h file to include */
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/*
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* Copyright (c) 1997-2014 Wind River Systems, Inc.
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*
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2017-01-19 09:01:01 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-04-11 07:44:37 +08:00
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*/
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2018-09-15 01:43:44 +08:00
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#ifndef ZEPHYR_INCLUDE_ARCH_CPU_H_
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#define ZEPHYR_INCLUDE_ARCH_CPU_H_
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2015-04-11 07:44:37 +08:00
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2015-10-09 18:20:52 +08:00
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#if defined(CONFIG_X86)
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2015-05-29 01:56:47 +08:00
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#include <arch/x86/arch.h>
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2015-06-06 10:27:08 +08:00
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#elif defined(CONFIG_ARM)
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2015-05-29 01:56:47 +08:00
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#include <arch/arm/arch.h>
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2015-06-06 10:27:49 +08:00
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#elif defined(CONFIG_ARC)
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2015-05-29 01:56:47 +08:00
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#include <arch/arc/arch.h>
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2016-04-22 05:47:09 +08:00
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#elif defined(CONFIG_NIOS2)
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#include <arch/nios2/arch.h>
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arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:30 +08:00
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#elif defined(CONFIG_RISCV32)
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#include <arch/riscv32/arch.h>
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2017-01-21 03:52:29 +08:00
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#elif defined(CONFIG_XTENSA)
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#include <arch/xtensa/arch.h>
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2017-10-03 22:31:55 +08:00
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#elif defined(CONFIG_ARCH_POSIX)
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#include <arch/posix/arch.h>
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2015-04-11 07:44:37 +08:00
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#else
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2015-06-06 10:33:49 +08:00
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#error "Unknown Architecture"
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2015-04-11 07:44:37 +08:00
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#endif
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2018-09-15 01:43:44 +08:00
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#endif /* ZEPHYR_INCLUDE_ARCH_CPU_H_ */
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