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zephyr/drivers/clock_control/clock_control_renesas_cpg_m...

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drivers: clock: rcar: Deploy a driver for each soc This commit rewrite renesas R-Car clock driver in order to be able to support any new SoC easier. This work is so creating a clock driver per soc alongside a common driver for all reneasas r-car boars. - drivers: create a driver per soc - create a common driver - create a common header used by soc & common driver - create a soc specific driver calling for common driver - dts: use new compatible - use old yaml as common yaml - create a new "child" yaml to define the new compatible field - change compatible in device tree As in Linux, the driver can support both r8a77951 and r8a77950 SoC's so we decided to name the new driver as in Linux with Zephyr prefix : "clock_control_r8a7795_cpg_mssr.c". Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-05-12 15:56:43 +08:00
/*
* Copyright (c) 2022 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
#define ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
#ifdef CONFIG_SOC_SERIES_RCAR_GEN3
/* Software Reset Clearing Register offsets */
#define SRSTCLR(i) (0x940 + (i) * 4)
/* CPG write protect offset */
#define CPGWPR 0x900
/* Realtime Module Stop Control Register offsets */
static const uint16_t mstpcr[] = {
0x110, 0x114, 0x118, 0x11c,
0x120, 0x124, 0x128, 0x12c,
0x980, 0x984, 0x988, 0x98c,
};
/* Software Reset Register offsets */
static const uint16_t srcr[] = {
0x0A0, 0x0A8, 0x0B0, 0x0B8,
0x0BC, 0x0C4, 0x1C8, 0x1CC,
0x920, 0x924, 0x928, 0x92C,
};
/* CAN-FD Clock Frequency Control Register */
#define CANFDCKCR 0x244
/* Clock stop bit */
#define CANFDCKCR_CKSTP BIT(8)
/* CANFD Clock */
#define CANFDCKCR_PARENT_CLK_RATE 800000000
#define CANFDCKCR_DIVIDER_MASK 0x1FF
drivers: pwm: add Renesas R-Car driver Add R-Car Gen3 PWM driver. Clock diviser is automatically adjusted according to requested period and duty-cycle in order to obtain as much accuracy as possible. Indeed, in order to improve PWM accurancy, the PWM clock has to fit the requested period. So use the given period_cycle to define if the clock as to be adapted. In such case, increase/decrease the clock diviser to adapt the period_cycle and be sure that it fits into the 10 bits counter of the PWM controller. Tested on H3ULCB on pwm0 and pwm4. Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
2022-01-28 01:14:13 +08:00
/* Peripherals Clocks */
#define S3D4_CLK_RATE 66600000 /* SCIF */
#define S0D12_CLK_RATE 66600000 /* PWM */
drivers: clock: rcar: Deploy a driver for each soc This commit rewrite renesas R-Car clock driver in order to be able to support any new SoC easier. This work is so creating a clock driver per soc alongside a common driver for all reneasas r-car boars. - drivers: create a driver per soc - create a common driver - create a common header used by soc & common driver - create a soc specific driver calling for common driver - dts: use new compatible - use old yaml as common yaml - create a new "child" yaml to define the new compatible field - change compatible in device tree As in Linux, the driver can support both r8a77951 and r8a77950 SoC's so we decided to name the new driver as in Linux with Zephyr prefix : "clock_control_r8a7795_cpg_mssr.c". Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-05-12 15:56:43 +08:00
#endif /* CONFIG_SOC_SERIES_RCAR_GEN3 */
void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val);
drivers/clock/rcar: Move ASSERT to module clock function ASSERT was failing when `r8a7795_cpg_mssr_start_stop` was called for a "core" clock. This ASSERT statement and "mstpcr" table of registers are only meant to be used when starting or stopping a "module" clock. Moved ASSERT statement to `rcar_cpg_mstp_clock_endisable` as well as "reg" & "bit" calculation. Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-07-11 22:47:56 +08:00
int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable);
drivers: clock: rcar: Deploy a driver for each soc This commit rewrite renesas R-Car clock driver in order to be able to support any new SoC easier. This work is so creating a clock driver per soc alongside a common driver for all reneasas r-car boars. - drivers: create a driver per soc - create a common driver - create a common header used by soc & common driver - create a soc specific driver calling for common driver - dts: use new compatible - use old yaml as common yaml - create a new "child" yaml to define the new compatible field - change compatible in device tree As in Linux, the driver can support both r8a77951 and r8a77950 SoC's so we decided to name the new driver as in Linux with Zephyr prefix : "clock_control_r8a7795_cpg_mssr.c". Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-05-12 15:56:43 +08:00
#endif /* ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_ */