zephyr/tests/kernel/usage/thread_runtime_stats/testcase.yaml

tests:
  kernel.usage:
    tags: kernel
# The following architectures are excluded as they have boards that
# exhibit precision timing anomalies related to emulation.
#     posix, riscv32, sparc
# The following architectures are exluded as the necessary
# thread runtime statistic hooks do not yet exist.
#     mips
    arch_exclude: posix sparc mips
# SMP is excluded as the test was only written for UP
    filter: not CONFIG_SMP
tests: runtime threads stats Adds tests to verify the gathering of thread runtime stats. Signed-off-by: Peter Mitsis <peter.mitsis@intel.com> 2022-04-20 22:18:11 +08:00			`tests:`
			`kernel.usage:`
			`tags: kernel`
			`# The following architectures are excluded as they have boards that`
			`# exhibit precision timing anomalies related to emulation.`
			`# posix, riscv32, sparc`
			`# The following architectures are exluded as the necessary`
			`# thread runtime statistic hooks do not yet exist.`
			`# mips`
tests/kernel/usage/thread_runtime_stats: relax precision test for RISC-V This commit relaxes the precision requirements for idle event statistic test when RISC-V machine timer driver is used. This is needed for some platforms (e.g. hifive1), for which the cycle count is too low to pass the checks where a percent deviation of peak cycles count is allowed. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> 2022-05-19 18:17:36 +08:00			`arch_exclude: posix sparc mips`
tests: runtime threads stats Adds tests to verify the gathering of thread runtime stats. Signed-off-by: Peter Mitsis <peter.mitsis@intel.com> 2022-04-20 22:18:11 +08:00			`# SMP is excluded as the test was only written for UP`
			`filter: not CONFIG_SMP`