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zephyr/dts/riscv/sifive/riscv64-fu540.dtsi

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soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 17:33:12 +08:00
/*
* Copyright (c) 2021 Katsuhiro Suzuki
*
* SPDX-License-Identifier: Apache-2.0
*/
dts: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all dts code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 17:02:05 +08:00
#include <zephyr/dt-bindings/gpio/gpio.h>
soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS. Rather than specify input clock for each peripheral individually, instead specify the relevant clocks in DTS. This will enable easier support for non-default coreclk on fe310 in a follow-up CL. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-01 01:51:54 +08:00
#include <freq.h>
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 17:33:12 +08:00
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
model = "sifive,FU540";
soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS. Rather than specify input clock for each peripheral individually, instead specify the relevant clocks in DTS. This will enable easier support for non-default coreclk on fe310 in a follow-up CL. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-01 01:51:54 +08:00
clocks {
coreclk: core-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(1000)>;
};
tlclk: tl-clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&coreclk>;
clock-div = <2>;
};
};
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 17:33:12 +08:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
dts: bindings: riscv: Don't use riscv, prefix for vendor compat In 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for sifive CPUs'), new compat strings for SiFive CPUs were added, but with riscv prefixes. Vendor-specific compats should just be prefixed with the vendor, so move that over here. Fixes: 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for sifive CPUs') Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 01:42:00 +08:00
compatible = "sifive,e51";
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 17:33:12 +08:00
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imac";
status = "okay";
hlic: interrupt-controller {
compatible = "riscv,cpu-intc";
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
#address-cells = <0>;
#interrupt-cells = <1>;
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 17:33:12 +08:00
interrupt-controller;
};
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
modeselect: rom@1000 {
compatible = "sifive,modeselect0";
reg = <0x1000 0x1000>;
reg-names = "mem";
};
maskrom: rom@10000 {
compatible = "sifive,maskrom0";
reg = <0x10000 0x8000>;
reg-names = "mem";
};
dtim: dtim@1000000 {
compatible = "sifive,dtim0";
reg = <0x1000000 0x2000>;
reg-names = "mem";
};
itim0: itim0@1800000 {
compatible = "sifive,itim0";
reg = <0x1800000 0x2000>;
reg-names = "mem";
};
itim1: itim1@1808000 {
compatible = "sifive,itim0";
reg = <0x1808000 0x7000>;
reg-names = "mem";
};
itim2: itim2@1810000 {
compatible = "sifive,itim0";
reg = <0x1810000 0x7000>;
reg-names = "mem";
};
itim3: itim3@1818000 {
compatible = "sifive,itim0";
reg = <0x1818000 0x7000>;
reg-names = "mem";
};
itim4: itim4@1820000 {
compatible = "sifive,itim0";
reg = <0x1820000 0x7000>;
reg-names = "mem";
};
clint: clint@2000000 {
dts: riscv: sifive: use sifive,clint0 Use the sifive,clint0 compatible instead of "riscv,clint0" and remove interrupt controller fields (clint compatible is used for its timer registers). Refer to the Linux or previous commits for more context. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 21:54:59 +08:00
compatible = "sifive,clint0";
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 17:33:12 +08:00
interrupts-extended = <&hlic 3 &hlic 7>;
reg = <0x2000000 0x10000>;
};
l2lim: l2lim@8000000 {
compatible = "sifive,l2lim0";
reg = <0x8000000 0x2000000>;
reg-names = "mem";
};
plic: interrupt-controller@c000000 {
compatible = "sifive,plic-1.0.0";
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
#address-cells = <0>;
#interrupt-cells = <2>;
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 17:33:12 +08:00
interrupt-controller;
interrupts-extended = <&hlic 11>;
reg = <0x0c000000 0x00002000
0x0c002000 0x001fe000
0x0c200000 0x03e00000>;
reg-names = "prio", "irq_en", "reg";
riscv,max-priority = <7>;
riscv,ndev = <52>;
};
uart0: serial@10010000 {
compatible = "sifive,uart0";
interrupt-parent = <&plic>;
interrupts = <4 1>;
reg = <0x10010000 0x1000>;
reg-names = "control";
status = "disabled";
};
uart1: serial@10011000 {
compatible = "sifive,uart0";
interrupt-parent = <&plic>;
interrupts = <5 1>;
reg = <0x10011000 0x1000>;
reg-names = "control";
status = "disabled";
};
spi0: spi@10040000 {
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <51 1>;
reg = <0x10040000 0x1000 0x20000000 0x10000000>;
reg-names = "control", "mem";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@10041000 {
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <52 1>;
reg = <0x10041000 0x1000>;
reg-names = "control";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi2: spi@10050000 {
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <6 1>;
reg = <0x10050000 0x1000>;
reg-names = "control";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
boards: riscv: hifive_unleashed: add GPIO support This patch adds GPIO and 96board LS (Low Speed)iexpansion connector support for SiFive HiFive Unleashed and also enables GPIO basic test. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2022-01-19 16:31:21 +08:00
gpio0: gpio@10060000 {
compatible = "sifive,gpio0";
gpio-controller;
interrupt-parent = <&plic>;
interrupts = <7 1>, <8 1>, <9 1>, <10 1>,
<11 1>, <12 1>, <13 1>, <14 1>,
<15 1>, <16 1>, <17 1>, <18 1>,
<19 1>, <20 1>, <21 1>, <22 1>;
reg = <0x10060000 0x1000>;
reg-names = "control";
status = "disabled";
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
soc: riscv: add initial support for SiFive Freedom U540 This patch adds support for SiFive Freedom U540 SoC. First version is minimum only using UART, SPI and DDR memory area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-06-09 17:33:12 +08:00
};
};