zephyr/soc/x86/ia32/linker.ld

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/*
* Copyright (c) 2011-2014, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-10 15:41:08 +08:00
*
* If XIP is turned on, board-level DTS must specify a flash region
* that doesn't overlap with sram0, so that DT_PHYS_LOAD_ADDR is set.
*/
#include <autoconf.h>
#include <generated_dts_board.h>
/* physical address where the kernel is loaded */
/* physical address of RAM */
#ifdef CONFIG_XIP
x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-10 15:41:08 +08:00
#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#else /* !CONFIG_XIP */
x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-10 15:41:08 +08:00
#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#endif /* CONFIG_XIP */
MEMORY
{
#ifdef CONFIG_XIP
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-10 15:41:08 +08:00
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
#else /* !CONFIG_XIP */
x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-10 15:41:08 +08:00
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
#endif /* CONFIG_XIP */
/*
* It doesn't matter where this region goes as it is stripped from the
* final ELF image. The address doesn't even have to be valid on the
* target. However, it shouldn't overlap any other regions.
*/
IDT_LIST : ORIGIN = 0xFFFF1000, LENGTH = 2K
}
#ifdef CONFIG_X86_LONGMODE
#include <arch/x86/intel64/linker.ld>
#else
#include <arch/x86/ia32/linker.ld>
#endif