130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
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/*
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* Copyright (c) 2018 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32_I2S_H_
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#define _STM32_I2S_H_
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#ifdef CONFIG_I2S_STM32_USE_PLLI2S_ENABLE
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#if defined(RCC_CFGR_I2SSRC)
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/* single selector for the I2S clock source (SEL_1 == SEL_2) */
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#define CLK_SEL_1 LL_RCC_I2S1_CLKSOURCE_PLLI2S
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#define CLK_SEL_2 LL_RCC_I2S1_CLKSOURCE_PLLI2S
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#else
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#if defined(RCC_DCKCFGR_I2SSRC)
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/* single selector for the I2S clock source (SEL_1 == SEL_2) */
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#define CLK_SEL_1 LL_RCC_I2S1_CLKSOURCE_PLL
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#define CLK_SEL_2 LL_RCC_I2S1_CLKSOURCE_PLL
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#else
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#if defined(RCC_DCKCFGR_I2S1SRC) && defined(RCC_DCKCFGR_I2S2SRC)
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/* double selector for the I2S clock source (SEL_1 != SEL_2) */
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#define CLK_SEL_1 LL_RCC_I2S1_CLKSOURCE_PLLI2S
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#define CLK_SEL_2 LL_RCC_I2S2_CLKSOURCE_PLLI2S
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#endif /* RCC_DCKCFGR_I2S1SRC && RCC_DCKCFGR_I2S2SRC */
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#endif /* RCC_DCKCFGR_I2SSRC */
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#endif /* RCC_CFGR_I2SSRC */
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#else
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#if defined(RCC_CFGR_I2SSRC)
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/* single selector for the I2S clock source (SEL_1 == SEL_2) */
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#define CLK_SEL_1 LL_RCC_I2S1_CLKSOURCE_PIN
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#define CLK_SEL_2 LL_RCC_I2S1_CLKSOURCE_PIN
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#else
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#if defined(RCC_DCKCFGR_I2SSRC)
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/* single selector for the I2S clock source (SEL_1 == SEL_2) */
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#define CLK_SEL_1 LL_RCC_I2S1_CLKSOURCE_PLLSRC
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#define CLK_SEL_2 LL_RCC_I2S1_CLKSOURCE_PLLSRC
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#else
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#if defined(RCC_DCKCFGR_I2S1SRC) && defined(RCC_DCKCFGR_I2S2SRC)
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/* double selector for the I2S clock source (SEL_1 != SEL_2) */
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#define CLK_SEL_1 LL_RCC_I2S1_CLKSOURCE_PLLSRC
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#define CLK_SEL_2 LL_RCC_I2S2_CLKSOURCE_PLLSRC
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#endif /* RCC_DCKCFGR_I2S1SRC && RCC_DCKCFGR_I2S2SRC */
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#endif /* RCC_DCKCFGR_I2SSRC */
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#endif /* RCC_CFGR_I2SSRC */
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#endif /* CONFIG_I2S_STM32_USE_PLLI2S_ENABLE */
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#ifdef CONFIG_SOC_SERIES_STM32F4X
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#define I2S1_DMA_NAME CONFIG_DMA_2_NAME
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#define I2S1_DMA_CHAN_RX 2
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#define I2S1_DMA_SLOT_RX 3
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#define I2S1_DMA_CHAN_TX 3
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#define I2S1_DMA_SLOT_TX 3
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#define I2S2_DMA_NAME CONFIG_DMA_1_NAME
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#define I2S2_DMA_CHAN_RX 3
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#define I2S2_DMA_SLOT_RX 0
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#define I2S2_DMA_CHAN_TX 4
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#define I2S2_DMA_SLOT_TX 0
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#define I2S3_DMA_NAME CONFIG_DMA_1_NAME
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#define I2S3_DMA_CHAN_RX 0
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#define I2S3_DMA_SLOT_RX 0
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#define I2S3_DMA_CHAN_TX 5
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#define I2S3_DMA_SLOT_TX 0
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#define I2S4_DMA_NAME CONFIG_DMA_2_NAME
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#define I2S4_DMA_CHAN_RX 0
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#define I2S4_DMA_SLOT_RX 4
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#define I2S4_DMA_CHAN_TX 1
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#define I2S4_DMA_SLOT_TX 4
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#define I2S5_DMA_NAME CONFIG_DMA_2_NAME
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#define I2S5_DMA_CHAN_RX 5
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#define I2S5_DMA_SLOT_RX 7
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#define I2S5_DMA_CHAN_TX 6
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#define I2S5_DMA_SLOT_TX 7
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#endif
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#define DEV_CFG(dev) \
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(const struct i2s_stm32_cfg * const)((dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct i2s_stm32_data *const)(dev)->driver_data)
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struct queue_item {
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void *mem_block;
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size_t size;
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};
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/* Minimal ring buffer implementation */
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struct ring_buf {
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struct queue_item *buf;
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u16_t len;
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u16_t head;
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u16_t tail;
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};
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/* Device constant configuration parameters */
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struct i2s_stm32_cfg {
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SPI_TypeDef *i2s;
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struct stm32_pclken pclken;
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u32_t i2s_clk_sel;
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void (*irq_config)(struct device *dev);
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};
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struct stream {
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s32_t state;
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struct k_sem sem;
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u32_t dma_channel;
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struct dma_config dma_cfg;
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struct i2s_config cfg;
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struct ring_buf mem_block_queue;
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void *mem_block;
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bool last_block;
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bool master;
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int (*stream_start)(struct stream *, struct device *dev);
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void (*stream_disable)(struct stream *, struct device *dev);
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void (*queue_drop)(struct stream *);
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};
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/* Device run time data */
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struct i2s_stm32_data {
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struct device *dev_dma;
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const char *dma_name;
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struct stream rx;
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struct stream tx;
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};
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#endif /* _STM32_I2S_H_ */
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