zephyr/soc/arm/xilinx_zynqmp/Kconfig.soc

# Copyright (c) 2019 Lexmark International, Inc.
# SPDX-License-Identifier: Apache-2.0

config SOC_XILINX_ZYNQMP
	bool "Xilinx ZynqMP"
	select CPU_CORTEX_R5
	select GIC_V1
	select MULTI_LEVEL_INTERRUPTS
	select 2ND_LEVEL_INTERRUPTS
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com> 2019-07-22 22:23:47 +08:00			`# Copyright (c) 2019 Lexmark International, Inc.`
			`# SPDX-License-Identifier: Apache-2.0`
kconfig: Clean up header comments and make them consistent Use this short header style in all Kconfig files: # <description> # <copyright> # <license> ... Also change all <description>s from # Kconfig[.extension] - Foo-related options to just # Foo-related options It's clear enough that it's about Kconfig. The <description> cleanup was done with this command, along with some manual cleanup (big letter at the start, etc.) git ls-files 'Kconfig' \| \ xargs sed -i -E '1 s/#\sKconfig[\w.-]\s-\s/# /' Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> 2019-11-01 20:45:29 +08:00
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com> 2019-07-22 22:23:47 +08:00			`config SOC_XILINX_ZYNQMP`
			`bool "Xilinx ZynqMP"`
			`select CPU_CORTEX_R5`
drivers: interrupt_controller: Refactor GIC configurations The current GIC configuration scheme is designed to support only one specific type and version of GIC (i.e. GIC-400 that implements the GICv2 interface). This commit adds a set of GIC version configuration symbols that can be selected by the SoC configuration to specify which version of GIC interface is implemented in the SoC. Signed-off-by: Stephanos Ioannidis <root@stephanos.io> 2019-12-19 11:41:44 +08:00			`select GIC_V1`
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com> 2019-07-22 22:23:47 +08:00			`select MULTI_LEVEL_INTERRUPTS`
			`select 2ND_LEVEL_INTERRUPTS`