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zephyr/soc/efinix/sapphire/Kconfig

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soc: riscv: Add initial support for Efinix Sapphire SoC - It's a riscv privilege spec SoC Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2023-03-21 03:44:20 +08:00
# Copyright (c) 2023 Efinix Inc.
# SPDX-License-Identifier: Apache-2.0
soc: riscv: efinix-sapphire: reorganize SoC folder Move things out from riscv-privileged, and convert to single SoC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-03 23:04:26 +08:00
config SOC_EFINIX_SAPPHIRE
soc: riscv: Add initial support for Efinix Sapphire SoC - It's a riscv privilege spec SoC Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2023-03-21 03:44:20 +08:00
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
soc: riscv: efinix-sapphire: reorganize SoC folder Move things out from riscv-privileged, and convert to single SoC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-03 23:04:26 +08:00
select RISCV
select RISCV_PRIVILEGED
soc: riscv: make RISCV_HAS_(C|P)LIC promptless These options are meant to be selected by SoC series supporting (C|P)LIC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-16 22:55:41 +08:00
select RISCV_HAS_PLIC
arch: riscv: imply XIP config pushed to SoC level 'imply XIP' pushed from arch/Kconfig/'config RISCV' to riscv SoCs Kconfig files to allow riscv SoCs having XIP enabled (or not) at SoC level Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-30 04:59:43 +08:00
imply XIP