128 lines
3.8 KiB
C
128 lines
3.8 KiB
C
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @brief Header file for Atmel SAM3 I2C/TWI driver.
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*
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* Contains register definitions for the TWI controller.
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* This uses TWI instead of I2C to align with the datasheet.
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*/
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#ifndef _DRIVERS_I2C_ATMEL_SAM3_H_
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#define _DRIVERS_I2C_ATMEL_SAM3_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Control Register
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*/
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#define TWI_CR_START (1 << 0) /* START for read */
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#define TWI_CR_STOP (1 << 1) /* Send STOP */
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#define TWI_CR_MSEN (1 << 2) /* Master enable */
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#define TWI_CR_MSDIS (1 << 3) /* Master disable */
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#define TWI_CR_SVEN (1 << 4) /* Slave enable */
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#define TWI_CR_SVDIS (1 << 5) /* Slave disable */
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#define TWI_CR_QUICK (1 << 6) /* SMBUS quick command */
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#define TWI_CR_SWRST (1 << 7) /* Software reset */
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/*
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* Master Mode Register
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*/
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#define TWI_MMR_MREAD (1 << 12) /* 0 for write, 1 for read */
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/* IADR is for internal address. This specifies how many bytes to use. */
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#define TWI_MMR_IADRSZ_POS (8)
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#define TWI_MMR_IADRSZ_MASK (3 << TWI_MMR_IADRSZ_POS)
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#define TWI_MMR_IADRSZ_1_BYTE (1 << 8)
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#define TWI_MMR_IADRSZ_2_BYTE (2 << 8)
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#define TWI_MMR_IADRSZ_3_BYTE (3 << 8)
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/* DADR is for destination (slave) address in master mode */
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#define TWI_MMR_DADR_POS (16)
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#define TWI_MMR_DADR_MASK (0x7F << TWI_MMR_DADR_POS)
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/*
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* Slave Mode Register
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*/
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#define TWI_MMR_SADR_POS (16)
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#define TWI_MMR_SADR_MASK (0x7F << TWI_MMR_DADR_POS)
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/*
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* Internal Address Register
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*/
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#define TWI_IADR_POS (0)
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#define TWI_IADR_MASK (0xFFFFFF << TWI_IADR_POS)
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/*
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* Clock Waveform Generator Register
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*/
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#define TWI_CWGR_CKDIV_POS (16)
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#define TWI_CWGR_CKDIV_MSGK (0x07 << TWI_CWGR_CKDIV_POS)
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#define TWI_CWGR_CHDIV_POS (8)
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#define TWI_CWGR_CHDIV_MASK (0xFF << TWI_CWGR_CHDIV_POS)
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#define TWI_CWGR_CLDIV_POS (0)
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#define TWI_CWGR_CLDIV_MASK (0xFF << TWI_CWGR_CLDIV_POS)
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/*
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* Status (SR),
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* Interrupt Enable (IER),
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* Interrupt Disable (IDR),
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* Interrupt Mask (IMR) registers
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*/
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#define TWI_IRQ_TXCOMP (1 << 0) /* Transfer complete */
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#define TWI_IRQ_RXRDY (1 << 1) /* RX ready */
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#define TWI_IRQ_TXRDY (1 << 2) /* TX ready */
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#define TWI_IRQ_SVREAD (1 << 3) /* Slave read */
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#define TWI_IRQ_SVACC (1 << 4) /* Slave access */
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#define TWI_IRQ_GACC (1 << 5) /* General call access */
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#define TWI_IRQ_OVRE (1 << 6) /* Overrun error */
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#define TWI_IRQ_NACK (1 << 8) /* No ACK */
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#define TWI_IRQ_ARBLST (1 << 9) /* Arbitration lost */
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#define TWI_IRQ_SCLWS (1 << 10) /* Clock wait state */
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#define TWI_IRQ_EOSACC (1 << 11) /* End of slave access */
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#define TWI_IRQ_ENDRX (1 << 12) /* End of RX buffer (PDC) */
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#define TWI_IRQ_ENDTX (1 << 13) /* End of TX buffer (PDC) */
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#define TWI_IRQ_RXBUFF (1 << 14) /* RX buffer full (PDC) */
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#define TWI_IRQ_TXBUFE (1 << 15) /* TX buffer full (PDC) */
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#define TWI_IRQ_PDC \
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(TWI_IRQ_ENDRX | TWI_IRQ_ENDTX | TWI_IRQ_RXBUFF | TWI_IRQ_TXBUFE)
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/* Bits to disable all interrupts */
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#define TWI_IRQ_DISABLE (0x0000FF77)
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/*
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* Receive Holding Register
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*/
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#define TWI_RHR_POS (0)
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#define TWI_RHR_MASK (0xFF << TWI_RHR_POS)
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/*
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* Transmit Holding Register
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*/
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#define TWI_THR_POS (0)
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#define TWI_THR_MASK (0xFF << TWI_THR_POS)
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVERS_I2C_ATMEL_SAM3H_ */
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