2021-08-13 06:11:17 +08:00
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/*
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* Copyright (c) 2021 Piotr Mienkowski
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief DAC driver for Atmel SAM MCU family.
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*
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* Remarks:
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* Only SAME70, SAMV71 series devices are currently supported. Please submit a
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* patch.
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*/
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#define DT_DRV_COMPAT atmel_sam_dac
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#include <errno.h>
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2022-05-06 16:25:46 +08:00
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#include <zephyr/sys/__assert.h>
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2021-08-13 06:11:17 +08:00
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#include <soc.h>
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2022-05-06 16:25:46 +08:00
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#include <zephyr/device.h>
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#include <zephyr/drivers/dac.h>
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#include <zephyr/drivers/pinctrl.h>
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2021-08-13 06:11:17 +08:00
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2022-05-06 16:25:46 +08:00
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#include <zephyr/logging/log.h>
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2021-08-13 06:11:17 +08:00
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LOG_MODULE_REGISTER(dac_sam, CONFIG_DAC_LOG_LEVEL);
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BUILD_ASSERT(IS_ENABLED(CONFIG_SOC_SERIES_SAME70) ||
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IS_ENABLED(CONFIG_SOC_SERIES_SAMV71),
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"Only SAME70, SAMV71 series devices are currently supported.");
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#define DAC_CHANNEL_NO 2
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/* Device constant configuration parameters */
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struct dac_sam_dev_cfg {
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Dacc *regs;
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2022-03-14 01:39:09 +08:00
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const struct pinctrl_dev_config *pcfg;
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2021-08-13 06:11:17 +08:00
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void (*irq_config)(void);
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uint8_t irq_id;
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uint8_t periph_id;
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uint8_t prescaler;
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};
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struct dac_channel {
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struct k_sem sem;
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};
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/* Device run time data */
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struct dac_sam_dev_data {
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struct dac_channel dac_channels[DAC_CHANNEL_NO];
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};
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2022-01-06 18:27:07 +08:00
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static void dac_sam_isr(const struct device *dev)
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2021-08-13 06:11:17 +08:00
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{
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2022-01-18 22:20:23 +08:00
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const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
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struct dac_sam_dev_data *const dev_data = dev->data;
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2021-08-13 06:11:17 +08:00
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Dacc *const dac = dev_cfg->regs;
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uint32_t int_stat;
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/* Retrieve interrupt status */
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int_stat = dac->DACC_ISR & dac->DACC_IMR;
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if ((int_stat & DACC_ISR_TXRDY0) != 0) {
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/* Disable Transmit Ready Interrupt */
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dac->DACC_IDR = DACC_IDR_TXRDY0;
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k_sem_give(&dev_data->dac_channels[0].sem);
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}
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if ((int_stat & DACC_ISR_TXRDY1) != 0) {
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/* Disable Transmit Ready Interrupt */
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dac->DACC_IDR = DACC_IDR_TXRDY1;
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k_sem_give(&dev_data->dac_channels[1].sem);
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}
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}
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static int dac_sam_channel_setup(const struct device *dev,
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const struct dac_channel_cfg *channel_cfg)
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{
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const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
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Dacc *const dac = dev_cfg->regs;
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if (channel_cfg->channel_id >= DAC_CHANNEL_NO) {
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return -EINVAL;
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}
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if (channel_cfg->resolution != 12) {
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return -ENOTSUP;
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}
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/* Enable Channel */
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dac->DACC_CHER = DACC_CHER_CH0 << channel_cfg->channel_id;
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return 0;
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}
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static int dac_sam_write_value(const struct device *dev, uint8_t channel,
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uint32_t value)
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{
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struct dac_sam_dev_data *const dev_data = dev->data;
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const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
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Dacc *const dac = dev_cfg->regs;
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if (channel >= DAC_CHANNEL_NO) {
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return -EINVAL;
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}
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if (dac->DACC_IMR & (DACC_IMR_TXRDY0 << channel)) {
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/* Attempting to send data on channel that's already in use */
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return -EINVAL;
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}
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k_sem_take(&dev_data->dac_channels[channel].sem, K_FOREVER);
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/* Trigger conversion */
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dac->DACC_CDR[channel] = DACC_CDR_DATA0(value);
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/* Enable Transmit Ready Interrupt */
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dac->DACC_IER = DACC_IER_TXRDY0 << channel;
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return 0;
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}
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static int dac_sam_init(const struct device *dev)
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{
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const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
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struct dac_sam_dev_data *const dev_data = dev->data;
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Dacc *const dac = dev_cfg->regs;
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int retval;
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/* Configure interrupts */
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dev_cfg->irq_config();
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/* Initialize semaphores */
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for (int i = 0; i < ARRAY_SIZE(dev_data->dac_channels); i++) {
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k_sem_init(&dev_data->dac_channels[i].sem, 1, 1);
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}
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/* Enable DAC clock in PMC */
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soc_pmc_peripheral_enable(dev_cfg->periph_id);
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2022-03-14 01:39:09 +08:00
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retval = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (retval < 0) {
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return retval;
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}
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2021-08-13 06:11:17 +08:00
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/* Set Mode Register */
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dac->DACC_MR = DACC_MR_PRESCALER(dev_cfg->prescaler);
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/* Enable module's IRQ */
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irq_enable(dev_cfg->irq_id);
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2022-03-16 03:13:24 +08:00
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LOG_INF("Device %s initialized", dev->name);
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return 0;
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}
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static const struct dac_driver_api dac_sam_driver_api = {
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.channel_setup = dac_sam_channel_setup,
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.write_value = dac_sam_write_value,
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};
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/* DACC */
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static void dacc_irq_config(void)
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{
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), dac_sam_isr,
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DEVICE_DT_INST_GET(0), 0);
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}
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2022-03-14 01:39:09 +08:00
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PINCTRL_DT_INST_DEFINE(0);
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static const struct dac_sam_dev_cfg dacc_sam_config = {
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.regs = (Dacc *)DT_INST_REG_ADDR(0),
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
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.irq_id = DT_INST_IRQN(0),
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.irq_config = dacc_irq_config,
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.periph_id = DT_INST_PROP(0, peripheral_id),
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.prescaler = DT_INST_PROP(0, prescaler),
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};
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static struct dac_sam_dev_data dacc_sam_data;
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DEVICE_DT_INST_DEFINE(0, dac_sam_init, NULL, &dacc_sam_data, &dacc_sam_config,
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2021-10-26 08:13:48 +08:00
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POST_KERNEL, CONFIG_DAC_INIT_PRIORITY,
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&dac_sam_driver_api);
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