2019-04-06 21:08:09 +08:00
|
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
|
2018-05-23 19:22:20 +08:00
|
|
|
zephyr_library()
|
2018-03-28 18:06:12 +08:00
|
|
|
|
2018-11-12 23:36:24 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_SPI_NOR spi_nor.c)
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 20:33:37 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_NORDIC_QSPI_NOR nrf_qspi_nor.c)
|
2019-04-18 20:55:30 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_FLASH_SIMULATOR flash_simulator.c)
|
2018-03-28 18:06:12 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_SPI_FLASH_W25QXXDV spi_flash_w25qxxdv.c)
|
|
|
|
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF soc_flash_nrf.c)
|
|
|
|
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_MCUX soc_flash_mcux.c)
|
|
|
|
zephyr_library_sources_ifdef(CONFIG_FLASH_PAGE_LAYOUT flash_page_layout.c)
|
|
|
|
zephyr_library_sources_ifdef(CONFIG_USERSPACE flash_handlers.c)
|
|
|
|
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM0 flash_sam0.c)
|
2018-11-05 04:41:22 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM flash_sam.c)
|
2018-03-28 18:06:12 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NIOS2_QSPI soc_flash_nios2_qspi.c)
|
2018-08-07 20:11:45 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_GECKO flash_gecko.c)
|
2019-05-22 23:07:50 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RV32M1 soc_flash_rv32m1.c)
|
2017-10-27 21:43:34 +08:00
|
|
|
|
2019-12-09 05:06:17 +08:00
|
|
|
if(CONFIG_SOC_FLASH_STM32)
|
2019-02-18 19:20:31 +08:00
|
|
|
zephyr_sources(flash_stm32.c)
|
|
|
|
|
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X flash_stm32f0x.c)
|
2019-07-30 16:21:30 +08:00
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X flash_stm32f1x.c)
|
2019-02-18 19:20:31 +08:00
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X flash_stm32f3x.c)
|
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X flash_stm32f4x.c)
|
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X flash_stm32f7x.c)
|
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X flash_stm32l4x.c)
|
2019-03-27 23:52:37 +08:00
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX flash_stm32wbx.c)
|
2019-07-05 21:02:21 +08:00
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X flash_stm32g0x.c)
|
2019-09-04 16:43:59 +08:00
|
|
|
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X flash_stm32g4x.c)
|
2017-10-27 21:43:34 +08:00
|
|
|
endif()
|
|
|
|
|
2018-12-17 17:46:13 +08:00
|
|
|
zephyr_include_directories_ifdef(
|
|
|
|
CONFIG_SOC_FLASH_NRF_RADIO_SYNC
|
|
|
|
${ZEPHYR_BASE}/subsys/bluetooth
|
|
|
|
${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic
|
|
|
|
)
|
2018-10-19 01:15:46 +08:00
|
|
|
|
2018-12-17 17:46:13 +08:00
|
|
|
zephyr_library_sources_ifdef(CONFIG_FLASH_SHELL flash_shell.c)
|