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zephyr/soc/riscv/openisa_rv32m1/wdog.S

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soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
/*
* Copyright (c) 2018 Foundries.io Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <linker/sections.h>
#include <toolchain.h>
riscv: use standard MSTATUS This is no longer needed, since all in-tree platforms are only using the standard mstatus formats. Remove it to avoid the complexity. Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-04 10:18:24 +08:00
#include <arch/cpu.h>
soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
/* Exports */
GTEXT(_WdogInit)
/* WDOG instance base address. */
#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
#define WDOG_BASE 0x4002A000 /* WDOG0 */
#else
#define WDOG_BASE 0x41026000 /* WDOG1 */
#endif
/* Register offsets. */
#define WDOG_CS_OFFSET 0x00
#define WDOG_CNT_OFFSET 0x04
#define WDOG_TOVAL_OFFSET 0x08
/* Watchdog unlock key. */
#define WDOG_CNT_UNLOCK 0xD928C520
/* TOVAL must be set when disabling watchdog after reset. */
#define WDOG_TOVAL_SET 0xFFFF
/* Disable the WDOG_CS[EN] bit. */
#define WDOG_CS_EN_DISABLED ~0x80
/* Set WDOG_CS[UPDATE] bit. */
#define WDOG_CS_UPDATE_ENABLED 0x20
/*
* Unlock and disable the watchdog, which is enabled by default.
*/
SECTION_FUNC(TEXT, _WdogInit)
/* Disable interrupts if they're on. This is timing-sensitive code. */
riscv: use standard MSTATUS This is no longer needed, since all in-tree platforms are only using the standard mstatus formats. Remove it to avoid the complexity. Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-04 10:18:24 +08:00
csrrc t0, mstatus, MSTATUS_IEN
soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
/* Get base address. */
li t1, WDOG_BASE
/* Unlock the watchdog. */
li t2, WDOG_CNT_UNLOCK
sw t2, WDOG_CNT_OFFSET(t1)
/* Disable the watchdog. Allow updates later. */
lw t2, WDOG_CS_OFFSET(t1)
andi t2, t2, WDOG_CS_EN_DISABLED
ori t2, t2, WDOG_CS_UPDATE_ENABLED
sw t2, WDOG_CS_OFFSET(t1)
/* This must also be done per reference manual. */
li t2, WDOG_TOVAL_SET
sw t2, WDOG_TOVAL_OFFSET(t1)
/* Re-enable interrupts if they were disabled. */
csrrs x0, mstatus, t0
ret