102 lines
1.6 KiB
Plaintext
102 lines
1.6 KiB
Plaintext
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <renesas/ra/ra8/r7fa8d1bhecbd.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include "ek_ra8d1-pinctrl.dtsi"
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/ {
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model = "Renesas EK-RA8D1";
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compatible = "renesas,ra8d1", "renesas,ra8";
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart9;
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zephyr,shell-uart = &uart9;
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};
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leds {
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compatible = "gpio-leds";
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led1: led1 {
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gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>;
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label = "LED1";
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};
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led2: led2 {
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gpios = <&ioport4 14 GPIO_ACTIVE_HIGH>;
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label = "LED2";
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};
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led3: led3 {
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gpios = <&ioport1 7 GPIO_ACTIVE_HIGH>;
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label = "LED3";
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};
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};
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aliases {
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led0 = &led1;
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};
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};
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&xtal {
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clock-frequency = <DT_FREQ_M(20)>;
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mosel = <0>;
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#clock-cells = <0>;
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status = "okay";
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};
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&subclk {
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status = "okay";
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};
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&pll {
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_2>;
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mul = <96 0>;
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divp = <RA_PLL_DIV_2>;
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freqp = <DT_FREQ_M(480)>;
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divq = <RA_PLL_DIV_2>;
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freqq = <DT_FREQ_M(480)>;
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divr = <RA_PLL_DIV_2>;
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freqr = <DT_FREQ_M(480)>;
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status = "okay";
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};
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&sciclk {
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clk_src = <RA_CLOCK_SOURCE_PLL1P>;
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clk_div = <RA_SCI_CLOCK_DIV_4>;
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status = "okay";
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};
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&ioport1 {
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status = "okay";
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};
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&ioport4 {
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status = "okay";
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};
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&ioport6 {
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status = "okay";
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};
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&sci0 {
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/* sci0 and spi0 cannot be enabled together */
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pinctrl-0 = <&sci9_default>;
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pinctrl-names = "default";
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};
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&sci9 {
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pinctrl-0 = <&sci9_default>;
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pinctrl-names = "default";
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status = "okay";
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uart9: uart {
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current-speed = <115200>;
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status = "okay";
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};
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};
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