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zephyr/arch/sparc/core/reset_trap.S

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arch: Add SPARC processor architecture SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:53:59 +08:00
/*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
asm: update files with <zephyr/...> include prefix Assembler files were not migrated with the new <zephyr/...> prefix. Note that the conversion has been scripted, refer to #45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 19:56:13 +08:00
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/sparc/sparc.h>
arch: Add SPARC processor architecture SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:53:59 +08:00
/* The trap table reset entry jumps to here. */
GTEXT(__sparc_trap_reset)
SECTION_FUNC(TEXT, __sparc_trap_reset)
set __sparc_trap_table, %g1
wr %g1, %tbr
SPARC: Keep interrupts disabled during kernel init This commit avoids enabling interrupts during Zephyr init. Details: Interrupts will be enabled only when the first thread starts or if arch_irq_unlock() is called before that. The logic is now: 1. Enable traps, disable interrupts globally 2. Initialize bss 3. Call _PrepC Use in-place memset() to avoid register window overflow and underflow traps. That is perhaps not the common scenario, but could happen with memset() implementation which contains SAVE instructions on a system with few register windows. The second, and more important, item this commit addresses is that it increases the processor interrupt level (priority) to highest. That is, it enters _PrepC with all maskable interrupts levels disabled. This fixes some cases where interrupts could be taken after z_clock_driver_init() while the system was still initializing. That seem to have occurred when clearing large thread stacks. The third thing is that we now start out with current window pointer 0 (PSR.CWP=0) instead of 1. It has no practical implication except for preparing for possible future support for systems with only two windows. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-11-26 19:16:22 +08:00
wr 2, %wim
wr PSR_PIL | PSR_S | PSR_PS | PSR_ET, %psr
arch: Add SPARC processor architecture SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:53:59 +08:00
/* NOTE: wrpsr above may have changed the current register window. */
SPARC: Keep interrupts disabled during kernel init This commit avoids enabling interrupts during Zephyr init. Details: Interrupts will be enabled only when the first thread starts or if arch_irq_unlock() is called before that. The logic is now: 1. Enable traps, disable interrupts globally 2. Initialize bss 3. Call _PrepC Use in-place memset() to avoid register window overflow and underflow traps. That is perhaps not the common scenario, but could happen with memset() implementation which contains SAVE instructions on a system with few register windows. The second, and more important, item this commit addresses is that it increases the processor interrupt level (priority) to highest. That is, it enters _PrepC with all maskable interrupts levels disabled. This fixes some cases where interrupts could be taken after z_clock_driver_init() while the system was still initializing. That seem to have occurred when clearing large thread stacks. The third thing is that we now start out with current window pointer 0 (PSR.CWP=0) instead of 1. It has no practical implication except for preparing for possible future support for systems with only two windows. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-11-26 19:16:22 +08:00
/* We are in the 3 instruction wrpsr delay so use global registers. */
set z_interrupt_stacks, %g2
set CONFIG_ISR_STACK_SIZE, %g4
add %g2, %g4, %g1
and %g1, 0xfffffff0, %l3
arch: Add SPARC processor architecture SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:53:59 +08:00
/*
* According to SPARC ABI, Chapter 3: The system marks the deepest
* stack frame by setting the frame pointer to zero. No other frame's
* %fp has a zero value.
*/
sub %l3, 96, %sp
clr %fp
clr %i7
#ifdef CONFIG_INIT_STACKS
SPARC: Keep interrupts disabled during kernel init This commit avoids enabling interrupts during Zephyr init. Details: Interrupts will be enabled only when the first thread starts or if arch_irq_unlock() is called before that. The logic is now: 1. Enable traps, disable interrupts globally 2. Initialize bss 3. Call _PrepC Use in-place memset() to avoid register window overflow and underflow traps. That is perhaps not the common scenario, but could happen with memset() implementation which contains SAVE instructions on a system with few register windows. The second, and more important, item this commit addresses is that it increases the processor interrupt level (priority) to highest. That is, it enters _PrepC with all maskable interrupts levels disabled. This fixes some cases where interrupts could be taken after z_clock_driver_init() while the system was still initializing. That seem to have occurred when clearing large thread stacks. The third thing is that we now start out with current window pointer 0 (PSR.CWP=0) instead of 1. It has no practical implication except for preparing for possible future support for systems with only two windows. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-11-26 19:16:22 +08:00
/* In-place memset() to avoid register window related traps. */
set 0xaaaaaaaa, %l0
mov %l0, %l1
1:
std %l0, [%g2]
add %g2, 8, %g2
cmp %g2, %l3
bne 1b
nop
arch: Add SPARC processor architecture SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:53:59 +08:00
#endif
call z_bss_zero
nop
arch: _PrepC -> z_prep_c Rename to use common naming for z_prep_c applied to all architectures. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-12-08 20:55:21 +08:00
call z_prep_c
arch: Add SPARC processor architecture SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:53:59 +08:00
nop
/* We halt the system by generating a "trap in trap" condition. */
GTEXT(arch_system_halt)
SECTION_FUNC(TEXT, arch_system_halt)
mov %o0, %g0
mov %g1, %g0
set 1, %g1
ta 0x00