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zephyr/soc/x86/apollo_lake/linker.ld

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arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
/*
* Copyright (c) 2011-2014, Wind River Systems, Inc.
arch/x86: initial Intel64 bootstrap framework This patch adds basic build infrastructure, definitions, a linker script, etc. to use the Zephyr and 0.10.1 SDK to build a 64-bit ELF binary suitable for use with GRUB to minimally bootstrap an Apollo Lake (e.g., UpSquared) board. The resulting binary can hardly be called a Zephyr kernel as it is lacking most of the glue logic, but it is a starting point to flesh those out in the x86 tree. The "kernel" builds with a few harmless warnings, both with GCC from the Zephyr SDK and with ICC (which is currently being worked on in a separate branch). These warnings are either related to pointer size differences (since this is an LP64 build) and/or dummy functions that will be replaced with working versions shortly. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-05 04:49:06 +08:00
* Copyright (c) 2019 Intel Corp.
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <autoconf.h>
#include <generated_dts_board.h>
arch/x86: initial Intel64 bootstrap framework This patch adds basic build infrastructure, definitions, a linker script, etc. to use the Zephyr and 0.10.1 SDK to build a 64-bit ELF binary suitable for use with GRUB to minimally bootstrap an Apollo Lake (e.g., UpSquared) board. The resulting binary can hardly be called a Zephyr kernel as it is lacking most of the glue logic, but it is a starting point to flesh those out in the x86 tree. The "kernel" builds with a few harmless warnings, both with GCC from the Zephyr SDK and with ICC (which is currently being worked on in a separate branch). These warnings are either related to pointer size differences (since this is an LP64 build) and/or dummy functions that will be replaced with working versions shortly. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-05 04:49:06 +08:00
#ifdef CONFIG_X86_LONGMODE
#include <arch/x86/intel64/linker.ld>
#else /* IA32 */
x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-10 15:41:08 +08:00
#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
MEMORY
{
x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-10 15:41:08 +08:00
RAM (wx) : ORIGIN = DT_PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
/*
* It doesn't matter where this region goes as it is stripped from the
* final ELF image. The address doesn't even have to be valid on the
* target. However, it shouldn't overlap any other regions.
*/
IDT_LIST : ORIGIN = 2K, LENGTH = 2K
}
arch/x86: move 32-bit linker script to ia32/ directory No functional changes. All references in soc/ are updated. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-29 00:41:39 +08:00
#include <arch/x86/ia32/linker.ld>
arch/x86/soc: add SoC configuration for Apollo Lake This adds the SoC configuration for Apollo Lake. This is based on the Atom configuration. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 09:37:14 +08:00
arch/x86: initial Intel64 bootstrap framework This patch adds basic build infrastructure, definitions, a linker script, etc. to use the Zephyr and 0.10.1 SDK to build a 64-bit ELF binary suitable for use with GRUB to minimally bootstrap an Apollo Lake (e.g., UpSquared) board. The resulting binary can hardly be called a Zephyr kernel as it is lacking most of the glue logic, but it is a starting point to flesh those out in the x86 tree. The "kernel" builds with a few harmless warnings, both with GCC from the Zephyr SDK and with ICC (which is currently being worked on in a separate branch). These warnings are either related to pointer size differences (since this is an LP64 build) and/or dummy functions that will be replaced with working versions shortly. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-05 04:49:06 +08:00
#endif /* CONFIG_X86_LONGMODE */