OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/arch/sparc/core/CMakeLists.txt

21 lines
373 B
CMake
Raw Normal View History

arch: Add SPARC processor architecture SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-17 02:53:59 +08:00
# SPDX-License-Identifier: Apache-2.0
zephyr_library()
zephyr_library_sources(
fatal.c
reset_trap.S
prep_c.c
switch.S
interrupt_trap.S
fault_trap.S
irq_manage.c
thread.c
window_trap.S
sw_trap_set_pil.S
trap_table_mvt.S
)
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
sparc: add support for thread local storage Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Register g7 is used to point to the thread data. Thread data is accessed with negative offsets from g7. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-10-27 19:31:41 +08:00
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)