119 lines
2.9 KiB
Plaintext
119 lines
2.9 KiB
Plaintext
|
/*
|
||
|
* Device Tree Source for the R-Car S4 (R8A779F0) SoC
|
||
|
*
|
||
|
* Copyright (C) 2023 EPAM Systems.
|
||
|
*
|
||
|
* SPDX-License-Identifier: Apache-2.0
|
||
|
*/
|
||
|
#include <arm64/armv8-a.dtsi>
|
||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||
|
#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
|
||
|
#include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
|
||
|
|
||
|
/ {
|
||
|
compatible = "renesas,r8a779f0";
|
||
|
#address-cells = <2>;
|
||
|
#size-cells = <2>;
|
||
|
interrupt-parent = <&gic>;
|
||
|
|
||
|
cpus {
|
||
|
#address-cells = <1>;
|
||
|
#size-cells = <0>;
|
||
|
|
||
|
a55: cpu@0 {
|
||
|
compatible = "arm,armv8";
|
||
|
reg = <0>;
|
||
|
device_type = "cpu";
|
||
|
enable-method = "psci";
|
||
|
};
|
||
|
};
|
||
|
|
||
|
psci {
|
||
|
compatible = "arm,psci-0.2";
|
||
|
method = "smc";
|
||
|
};
|
||
|
|
||
|
arch_timer: timer {
|
||
|
compatible = "arm,armv8-timer";
|
||
|
interrupt-parent = <&gic>;
|
||
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
|
||
|
<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
|
||
|
<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
|
||
|
<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||
|
};
|
||
|
|
||
|
reg_3p3v: regulator_3p3v {
|
||
|
compatible = "regulator-fixed";
|
||
|
regulator-name = "reg_3p3v";
|
||
|
regulator-min-microvolt = <3300000>;
|
||
|
regulator-max-microvolt = <3300000>;
|
||
|
regulator-always-on;
|
||
|
regulator-boot-on;
|
||
|
status = "okay";
|
||
|
};
|
||
|
|
||
|
reg_1p8v: regulator_1p8v {
|
||
|
compatible = "regulator-fixed";
|
||
|
regulator-name = "reg_1p8v";
|
||
|
regulator-min-microvolt = <1800000>;
|
||
|
regulator-max-microvolt = <1800000>;
|
||
|
regulator-always-on;
|
||
|
regulator-boot-on;
|
||
|
status = "okay";
|
||
|
};
|
||
|
|
||
|
soc: soc {
|
||
|
compatible = "simple-bus";
|
||
|
interrupt-parent = <&gic>;
|
||
|
|
||
|
#address-cells = <2>;
|
||
|
#size-cells = <2>;
|
||
|
ranges;
|
||
|
|
||
|
gic: interrupt-controller@f1000000 {
|
||
|
compatible = "arm,gic-600", "arm,gic-v3", "arm,gic";
|
||
|
#interrupt-cells = <4>;
|
||
|
#address-cells = <0>;
|
||
|
interrupt-controller;
|
||
|
reg = <0 0xf1000000 0 0x20000>,
|
||
|
<0 0xf1060000 0 0x110000>;
|
||
|
status = "okay";
|
||
|
};
|
||
|
|
||
|
cpg: clock-controller@e6150000 {
|
||
|
compatible = "renesas,r8a779f0-cpg-mssr";
|
||
|
reg = <0 0xe6150000 0 0x4000>;
|
||
|
#clock-cells = <2>;
|
||
|
#power-domain-cells = <0>;
|
||
|
#reset-cells = <1>;
|
||
|
};
|
||
|
|
||
|
mmc0: mmc@ee140000 {
|
||
|
compatible = "renesas,rcar-mmc";
|
||
|
reg = <0 0xee140000 0 0x2000>;
|
||
|
vmmc-supply = <®_3p3v>;
|
||
|
vqmmc-supply = <®_1p8v>;
|
||
|
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||
|
clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
|
||
|
max-bus-freq = <200000000>;
|
||
|
status = "disabled";
|
||
|
};
|
||
|
|
||
|
pfc: pin-controller@e6050000 {
|
||
|
compatible = "renesas,rcar-pfc";
|
||
|
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
|
||
|
<0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>,
|
||
|
<0 0xdfd90000 0 0x16c>, <0 0xdfd90800 0 0x16c>,
|
||
|
<0 0xdfd91000 0 0x16c>, <0 0xdfd91800 0 0x16c>;
|
||
|
};
|
||
|
|
||
|
hscif0: serial@e6540000 {
|
||
|
compatible = "renesas,rcar-hscif";
|
||
|
reg = <0 0xe6540000 0 0x60>;
|
||
|
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||
|
clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>;
|
||
|
status = "disabled";
|
||
|
};
|
||
|
};
|
||
|
};
|