2021-10-19 20:06:33 +08:00
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# Copyright (c) 2021 ATL-Electronics
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# SPDX-License-Identifier: Apache-2.0
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if(CONFIG_HAS_GD32_HAL)
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2021-11-01 18:06:48 +08:00
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string(TOUPPER ${CONFIG_SOC} gd32_soc_uc)
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2021-10-19 20:06:33 +08:00
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2021-11-11 07:00:38 +08:00
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set(gd32_soc_dir ${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/${CONFIG_SOC_SERIES})
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2024-01-02 19:11:01 +08:00
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if(CONFIG_ARM)
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2021-10-23 16:06:46 +08:00
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set(gd32_soc_sys_dir ${gd32_soc_dir}/cmsis/gd/${CONFIG_SOC_SERIES})
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2024-01-02 19:11:01 +08:00
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elseif(CONFIG_RISCV)
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2021-10-23 16:06:46 +08:00
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set(gd32_soc_sys_dir ${gd32_soc_dir}/riscv)
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zephyr_include_directories(${gd32_soc_dir}/riscv/drivers)
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endif()
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2021-10-19 20:06:33 +08:00
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set(gd32_std_dir ${gd32_soc_dir}/standard_peripheral)
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2021-11-11 07:00:38 +08:00
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set(gd32_std_src_dir ${gd32_std_dir}/source)
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2021-10-19 20:06:33 +08:00
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2021-11-01 18:06:48 +08:00
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zephyr_library_named(hal_gigadevice)
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2021-11-01 18:48:22 +08:00
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zephyr_compile_definitions(${gd32_soc_uc})
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2021-11-01 18:06:48 +08:00
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2021-10-23 16:06:46 +08:00
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# The header files of GigaDevice firmware are reference HXTAL_VALUE.
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# The HXTAL_VALUE has the possibility of being referenced from any files
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# via that header files.
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# Therefore, we need to define HXTAL_VALUE for all compilations.
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if(${CONFIG_GD32_HXTAL_8MHZ})
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zephyr_compile_definitions(HXTAL_VALUE=8000000 HXTAL_VALUE_25M=8000000)
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elseif(${CONFIG_GD32_HXTAL_25MHZ})
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zephyr_compile_definitions(HXTAL_VALUE=25000000 HXTAL_VALUE_8M=25000000)
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endif()
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2022-07-07 23:50:04 +08:00
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if(CONFIG_GD32_HAS_IRC_32K)
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zephyr_compile_definitions(IRC32K_VALUE=${CONFIG_GD32_LOW_SPEED_IRC_FREQUENCY})
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endif()
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if(CONFIG_GD32_HAS_IRC_40K)
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zephyr_compile_definitions(IRC40K_VALUE=${CONFIG_GD32_LOW_SPEED_IRC_FREQUENCY})
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endif()
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2022-06-17 07:09:03 +08:00
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# GD32E50X series HAL public headers require extra definitions
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if(${CONFIG_SOC_SERIES_GD32E50X})
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zephyr_compile_definitions(GD32E50X)
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if (${CONFIG_SOC_GD32E507})
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zephyr_compile_definitions(GD32E50X_CL)
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endif()
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endif()
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2023-01-09 20:40:21 +08:00
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# GD32A50X series HAL public headers require extra definitions
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if(${CONFIG_SOC_SERIES_GD32A50X})
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zephyr_compile_definitions(GD32A50X)
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endif()
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2021-10-19 20:06:33 +08:00
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# Global includes to be used outside hal_gigadevice
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2021-10-23 16:06:46 +08:00
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zephyr_include_directories(${gd32_soc_sys_dir}/include)
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2021-11-11 07:00:38 +08:00
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zephyr_include_directories(${gd32_std_dir}/include)
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2021-11-02 04:41:06 +08:00
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zephyr_include_directories(${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/include)
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2022-06-01 18:35:35 +08:00
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zephyr_include_directories(${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/common_include)
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2021-10-19 20:06:33 +08:00
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2021-10-23 16:06:46 +08:00
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zephyr_library_sources(${gd32_soc_sys_dir}/source/system_${CONFIG_SOC_SERIES}.c)
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2021-11-01 18:06:48 +08:00
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2022-06-17 06:23:03 +08:00
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_ADC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_adc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_BKP ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_bkp.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_CAN ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_can.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_CMP ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_cmp.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_CEC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_cec.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_CRC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_crc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_CTC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_ctc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_DAC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dac.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_DBG ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dbg.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_DCI ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dci.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_DMA ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dma.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_ENET ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_enet.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXMC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_exmc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXTI ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_exti.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_FMC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_fmc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_FWDGT ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_fwdgt.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_GPIO ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_gpio.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_I2C ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_i2c.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_IPA ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_ipa.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_IREF ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_iref.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_MISC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_misc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_PMU ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_pmu.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_RCU ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_rcu.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_RTC ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_rtc.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_SDIO ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_sdio.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_SHRTIMER ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_shrtimer.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_SPI ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_spi.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_SYSCFG ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_syscfg.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_TIMER ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_timer.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_TLI ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_tli.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_TMU ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_tmu.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_TRNG ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_trng.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_TSI ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_tsi.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_USART ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_usart.c)
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zephyr_library_sources_ifdef(CONFIG_USE_GD32_WWDGT ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_wwdgt.c)
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2021-10-19 20:06:33 +08:00
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endif()
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