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zephyr/drivers/interrupt_controller/ioapic_priv.h

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quark_se: apic: work around EOI forwarding issue Quark SE Lakemont core has a hardware bug where the LOAPIC does not properly notify the IOAPIC to clear the IRR bit for level- triggered interrupts. This patch introduces a workaround where the vector ID of the in-service interrupt is manually written to the IOAPIC_EOI register, resulting in the bit being cleared. Unfortunately, in the context where EOI happens it's very difficult to identify which IRQ line is being serviced, so this is done unconditionally for all interrupts vectors whether they are registered in the IOAPIC RTE table or not. Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-11 06:43:10 +08:00
/* ioapic_priv.h - private IOAPIC APIs */
/*
* Copyright (c) 2012-2015 Wind River Systems, Inc.
* Copyright (c) 2015 Intel Corporation
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
* SPDX-License-Identifier: Apache-2.0
quark_se: apic: work around EOI forwarding issue Quark SE Lakemont core has a hardware bug where the LOAPIC does not properly notify the IOAPIC to clear the IRR bit for level- triggered interrupts. This patch introduces a workaround where the vector ID of the in-service interrupt is manually written to the IOAPIC_EOI register, resulting in the bit being cleared. Unfortunately, in the context where EOI happens it's very difficult to identify which IRQ line is being serviced, so this is done unconditionally for all interrupts vectors whether they are registered in the IOAPIC RTE table or not. Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-11 06:43:10 +08:00
*/
headers: Fix headers across the project Any word started with underscore followed by and uppercase letter or a second underscore is a reserved word according with C99. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-15 01:43:44 +08:00
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IOAPIC_PRIV_H_
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IOAPIC_PRIV_H_
quark_se: apic: work around EOI forwarding issue Quark SE Lakemont core has a hardware bug where the LOAPIC does not properly notify the IOAPIC to clear the IRR bit for level- triggered interrupts. This patch introduces a workaround where the vector ID of the in-service interrupt is manually written to the IOAPIC_EOI register, resulting in the bit being cleared. Unfortunately, in the context where EOI happens it's very difficult to identify which IRQ line is being serviced, so this is done unconditionally for all interrupts vectors whether they are registered in the IOAPIC RTE table or not. Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-11 06:43:10 +08:00
/* IO APIC direct register offsets */
#define IOAPIC_IND 0x00 /* Index Register */
#define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
#define IOAPIC_IRQPA 0x20 /* IRQ Pin Assertion Register */
#define IOAPIC_EOI 0x40 /* EOI Register */
/* IO APIC indirect register offset */
#define IOAPIC_ID 0x00 /* IOAPIC ID */
#define IOAPIC_VERS 0x01 /* IOAPIC Version */
#define IOAPIC_ARB 0x02 /* IOAPIC Arbitration ID */
#define IOAPIC_BOOT 0x03 /* IOAPIC Boot Configuration */
#define IOAPIC_REDTBL 0x10 /* Redirection Table (24 * 64bit) */
/* Interrupt delivery type */
#define IOAPIC_DT_APIC 0x0 /* APIC serial bus */
#define IOAPIC_DT_FS 0x1 /* Front side bus message*/
/* Version register bits */
#define IOAPIC_MRE_MASK 0x00ff0000 /* Max Red. entry mask */
#define IOAPIC_PRQ 0x00008000 /* this has IRQ reg */
#define IOAPIC_VERSION 0x000000ff /* version number */
/* Redirection table entry number */
#define MAX_REDTABLE_ENTRIES 24
/* Redirection table entry bits: upper 32 bit */
#define IOAPIC_DESTINATION 0xff000000
/* Redirection table entry bits: lower 32 bit */
#define IOAPIC_VEC_MASK 0x000000ff
#endif