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zephyr/dts/riscv/virt.dtsi

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soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
/*
* Copyright (c) 2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This file is based on:
* qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256
* dtc virt.dtb > virt.dtsi
*/
/dts-v1/;
/ {
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
compatible = "riscv-virtio";
model = "riscv-virtio,qemu";
flash@20000000 {
bank-width = < 0x04 >;
reg = < 0x20000000 0x2000000 0x22000000 0x2000000 >;
compatible = "cfi-flash";
};
uart0: uart@10000000 {
interrupts = < 0x0a 1 >;
interrupt-parent = < &plic >;
clock-frequency = < 0x384000 >;
reg = < 0x10000000 0x100 >;
compatible = "ns16550";
reg-shift = < 0 >;
};
cpus {
#address-cells = < 0x01 >;
#size-cells = < 0x00 >;
timebase-frequency = < 10000000 >;
cpu@0 {
device_type = "cpu";
reg = < 0x00 >;
status = "okay";
compatible = "riscv";
hlic0: interrupt-controller {
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
compatible = "riscv,cpu-intc";
#address-cells = <0>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
reg = < 0x01 >;
status = "okay";
compatible = "riscv";
hlic1: interrupt-controller {
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
compatible = "riscv,cpu-intc";
#address-cells = <0>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@2 {
device_type = "cpu";
reg = < 0x02 >;
status = "okay";
compatible = "riscv";
hlic2: interrupt-controller {
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
compatible = "riscv,cpu-intc";
#address-cells = <0>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@3 {
device_type = "cpu";
reg = < 0x03 >;
status = "okay";
compatible = "riscv";
hlic3: interrupt-controller {
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
compatible = "riscv,cpu-intc";
#address-cells = <0>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@4 {
device_type = "cpu";
reg = < 0x04 >;
status = "okay";
compatible = "riscv";
hlic4: interrupt-controller {
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
compatible = "riscv,cpu-intc";
#address-cells = <0>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@5 {
device_type = "cpu";
reg = < 0x05 >;
status = "okay";
compatible = "riscv";
hlic5: interrupt-controller {
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
compatible = "riscv,cpu-intc";
#address-cells = <0>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@6 {
device_type = "cpu";
reg = < 0x06 >;
status = "okay";
compatible = "riscv";
hlic6: interrupt-controller {
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
compatible = "riscv,cpu-intc";
#address-cells = <0>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@7 {
device_type = "cpu";
reg = < 0x07 >;
status = "okay";
compatible = "riscv";
hlic7: interrupt-controller {
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
compatible = "riscv,cpu-intc";
#address-cells = <0>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
};
ram0: memory@80000000 {
device_type = "memory";
reg = < 0x80000000 0x10000000 >;
};
soc {
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
compatible = "simple-bus";
ranges;
plic: interrupt-controller@c000000 {
riscv,max-priority = <7>;
riscv,ndev = < 0x35 >;
reg = <0x0c000000 0x00002000
0x0c002000 0x001fe000
0x0c200000 0x03e00000>;
reg-names = "prio", "irq_en", "reg";
interrupts-extended = <
&hlic0 0x0b &hlic0 0x09
&hlic1 0x0b &hlic1 0x09
&hlic2 0x0b &hlic2 0x09
&hlic3 0x0b &hlic3 0x09
&hlic4 0x0b &hlic4 0x09
&hlic5 0x0b &hlic5 0x09
&hlic6 0x0b &hlic6 0x09
&hlic7 0x0b &hlic7 0x09
>;
interrupt-controller;
compatible = "sifive,plic-1.0.0";
#address-cells = < 0x00 >;
dts: riscv: add #address-cells to all interrupt controllers This mirrors #36499 and other PRs that added them for other architectures. This silences a large number of dtc warnings due to the missing property. It seems reasonable to require an address-cells property since any interrupt controller could be the parent of an interrupt-map. The only device actually using interrupt-maps is neorv32, and it needs an address-cells of 2 (since this is the default if none is specified it worked like that before this change). While I touched this, I reordered the properties for consistency across boards, but there's a lot of variance here already. Signed-off-by: Olof Johansson <olof@lixom.net>
2022-06-15 02:51:55 +08:00
#interrupt-cells = < 0x02 >;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
};
clint@2000000 {
dts: riscv: virt: use sifive,clint0 Use the sifive,clint0 compatible instead of "riscv,clint0" and remove interrupt controller fields (clint compatible is used for its timer registers). Refer to the Linux or previous commits for more context. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 21:58:08 +08:00
compatible = "sifive,clint0";
reg = <0x2000000 0x10000>;
interrupts-extended = <&hlic0 0x03 &hlic0 0x07
&hlic1 0x03 &hlic1 0x07
&hlic2 0x03 &hlic2 0x07
&hlic3 0x03 &hlic3 0x07
&hlic4 0x03 &hlic4 0x07
&hlic5 0x03 &hlic5 0x07
&hlic6 0x03 &hlic6 0x07
&hlic7 0x03 &hlic7 0x07>;
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 01:54:43 +08:00
};
};
};