zephyr/soc/xtensa/esp32/dts_fixup.h

/*
 * Copyright (c) 2018 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* SoC level DTS fixup file */

#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
#define CONFIG_ENTROPY_NAME DT_INST_0_ESPRESSIF_ESP32_TRNG_LABEL
/* End of SoC Level DTS fixup file */
arch: xtensa: Get CPU clock frequency from DTS The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no> 2019-04-11 20:28:52 +08:00			`/*`
			`* Copyright (c) 2018 Nordic Semiconductor ASA`
			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`

			`/* SoC level DTS fixup file */`

			`#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY`
esp32: drivers: Add Entropy Device tree support - Add TRNG module to esp32.dtsi - Updated the note about TRNG register address Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com> 2019-10-22 16:04:13 +08:00			`#define CONFIG_ENTROPY_NAME DT_INST_0_ESPRESSIF_ESP32_TRNG_LABEL`
arch: xtensa: Get CPU clock frequency from DTS The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no> 2019-04-11 20:28:52 +08:00			`/* End of SoC Level DTS fixup file */`