89 lines
2.0 KiB
Plaintext
89 lines
2.0 KiB
Plaintext
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/*
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* Device Tree Source for the R-Car H3 (R8A77951) SoC
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*
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* Copyright (C) 2023 EPAM Systems.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm64/armv8-a.dtsi>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
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#include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
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/ {
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compatible = "renesas,r8a77951";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a57_0: cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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};
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400", "arm,gic" ;
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#interrupt-cells = <4>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1010000 0 0x1000>,
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<0 0xf1020000 0 0x20000>;
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status = "okay";
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7795-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,rcar-pfc";
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reg = <0 0xe6060000 0 0x50c>;
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,rcar-scif";
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reg = <0 0xe6e88000 0 0x64>;
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interrupt-parent = <&gic>;
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clocks = <&cpg CPG_MOD 310>,
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<&cpg CPG_CORE R8A7795_CLK_S3D4>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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current-speed = <115200>;
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interrupt-names = "irq_0";
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status = "disabled";
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};
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};
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};
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