2020-04-23 17:38:06 +08:00
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/*
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* Copyright (c) 2020 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef DMAMUX_STM32_H_
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#define DMAMUX_STM32_H_
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/* this is the configuration of one dmamux channel */
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struct dmamux_stm32_channel {
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2020-05-01 02:33:38 +08:00
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const struct device *dev_dma; /* pointer to the associated dma instance */
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2020-05-28 00:26:57 +08:00
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uint8_t dma_id; /* ref of the associated dma stream for this instance */
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2020-04-23 17:38:06 +08:00
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};
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/* the table of all the dmamux channel */
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struct dmamux_stm32_data {
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struct dmamux_stm32_channel *mux_channels;
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void *callback_arg;
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2020-05-28 00:26:57 +08:00
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void (*dmamux_callback)(void *arg, uint32_t id,
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2020-04-23 17:38:06 +08:00
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int error_code);
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};
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/* this is the configuration of the dmamux IP */
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struct dmamux_stm32_config {
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struct stm32_pclken pclken;
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2020-05-28 00:26:57 +08:00
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uint32_t base;
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uint8_t channel_nb; /* total nb of channels */
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uint8_t gen_nb; /* total nb of Request generator */
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uint8_t req_nb; /* total nb of Peripheral Request inputs */
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2020-04-23 17:38:06 +08:00
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};
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2020-05-28 00:26:57 +08:00
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uint32_t table_ll_channel[] = {
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2020-04-23 17:38:06 +08:00
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LL_DMAMUX_CHANNEL_0,
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LL_DMAMUX_CHANNEL_1,
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LL_DMAMUX_CHANNEL_2,
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LL_DMAMUX_CHANNEL_3,
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LL_DMAMUX_CHANNEL_4,
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#if defined(LL_DMAMUX_CHANNEL_5)
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LL_DMAMUX_CHANNEL_5,
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#endif /* LL_DMAMUX_CHANNEL_5 */
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#if defined(LL_DMAMUX_CHANNEL_6)
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LL_DMAMUX_CHANNEL_6,
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#endif /* LL_DMAMUX_CHANNEL_6 */
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#if defined(LL_DMAMUX_CHANNEL_7)
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LL_DMAMUX_CHANNEL_7,
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#endif /* LL_DMAMUX_CHANNEL_7 */
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#if defined(LL_DMAMUX_CHANNEL_8)
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LL_DMAMUX_CHANNEL_8,
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#endif /* LL_DMAMUX_CHANNEL_8 */
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#if defined(LL_DMAMUX_CHANNEL_9)
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LL_DMAMUX_CHANNEL_9,
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#endif /* LL_DMAMUX_CHANNEL_9 */
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#if defined(LL_DMAMUX_CHANNEL_10)
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LL_DMAMUX_CHANNEL_10,
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#endif /* LL_DMAMUX_CHANNEL_10 */
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#if defined(LL_DMAMUX_CHANNEL_11)
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LL_DMAMUX_CHANNEL_11,
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#endif /* LL_DMAMUX_CHANNEL_11 */
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#if defined(LL_DMAMUX_CHANNEL_12)
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LL_DMAMUX_CHANNEL_12,
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#endif /* LL_DMAMUX_CHANNEL_12 */
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#if defined(LL_DMAMUX_CHANNEL_13)
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LL_DMAMUX_CHANNEL_13,
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#endif /* LL_DMAMUX_CHANNEL_13 */
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#if defined(LL_DMAMUX_CHANNEL_14)
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LL_DMAMUX_CHANNEL_14,
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#endif /* LL_DMAMUX_CHANNEL_14 */
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#if defined(LL_DMAMUX_CHANNEL_15)
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LL_DMAMUX_CHANNEL_15,
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#endif /* LL_DMAMUX_CHANNEL_15 */
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};
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2020-05-28 00:26:57 +08:00
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uint32_t (*func_ll_is_active_so[])(DMAMUX_Channel_TypeDef *DMAMUXx) = {
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2020-04-23 17:38:06 +08:00
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LL_DMAMUX_IsActiveFlag_SO0,
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LL_DMAMUX_IsActiveFlag_SO1,
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LL_DMAMUX_IsActiveFlag_SO2,
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LL_DMAMUX_IsActiveFlag_SO3,
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LL_DMAMUX_IsActiveFlag_SO4,
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LL_DMAMUX_IsActiveFlag_SO5,
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#if defined(DMAMUX_CSR_SOF6)
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LL_DMAMUX_IsActiveFlag_SO6,
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#endif /* DMAMUX_CSR_SOF6 */
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#if defined(DMAMUX_CSR_SOF7)
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LL_DMAMUX_IsActiveFlag_SO7,
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#endif /* DMAMUX_CSR_SOF7 */
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#if defined(DMAMUX_CSR_SOF8)
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LL_DMAMUX_IsActiveFlag_SO8,
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#endif /* DMAMUX_CSR_SOF8 */
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#if defined(DMAMUX_CSR_SOF9)
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LL_DMAMUX_IsActiveFlag_SO9,
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#endif /* DMAMUX_CSR_SOF9 */
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#if defined(DMAMUX_CSR_SOF10)
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LL_DMAMUX_IsActiveFlag_SO10,
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#endif /* DMAMUX_CSR_SOF10 */
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#if defined(DMAMUX_CSR_SOF11)
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LL_DMAMUX_IsActiveFlag_SO11,
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#endif /* DMAMUX_CSR_SOF11 */
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#if defined(DMAMUX_CSR_SOF12)
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LL_DMAMUX_IsActiveFlag_SO12,
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#endif /* DMAMUX_CSR_SOF12 */
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#if defined(DMAMUX_CSR_SOF130)
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LL_DMAMUX_IsActiveFlag_SO13,
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#endif /* DMAMUX_CSR_SOF130 */
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#if defined(DMAMUX_CSR_SOF14)
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LL_DMAMUX_IsActiveFlag_SO14,
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#endif /* DMAMUX_CSR_SOF14 */
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#if defined(DMAMUX_CSR_SOF15)
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LL_DMAMUX_IsActiveFlag_SO15,
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#endif /* DMAMUX_CSR_SOF15 */
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};
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void (*func_ll_clear_so[])(DMAMUX_Channel_TypeDef *DMAMUXx) = {
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LL_DMAMUX_ClearFlag_SO0,
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LL_DMAMUX_ClearFlag_SO1,
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LL_DMAMUX_ClearFlag_SO2,
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LL_DMAMUX_ClearFlag_SO3,
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LL_DMAMUX_ClearFlag_SO4,
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LL_DMAMUX_ClearFlag_SO5,
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#if defined(DMAMUX_CSR_SOF6)
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LL_DMAMUX_ClearFlag_SO6,
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#endif /* DMAMUX_CSR_SOF6 */
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#if defined(DMAMUX_CSR_SOF7)
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LL_DMAMUX_ClearFlag_SO7,
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#endif /* DMAMUX_CSR_SOF7 */
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#if defined(DMAMUX_CSR_SOF8)
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LL_DMAMUX_ClearFlag_SO8,
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#endif /* DMAMUX_CSR_SOF8 */
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#if defined(DMAMUX_CSR_SOF9)
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LL_DMAMUX_ClearFlag_SO9,
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#endif /* DMAMUX_CSR_SOF9 */
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#if defined(DMAMUX_CSR_SOF10)
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LL_DMAMUX_ClearFlag_SO10,
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#endif /* DMAMUX_CSR_SOF10 */
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#if defined(DMAMUX_CSR_SOF11)
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LL_DMAMUX_ClearFlag_SO11,
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#endif /* DMAMUX_CSR_SOF11 */
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#if defined(DMAMUX_CSR_SOF12)
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LL_DMAMUX_ClearFlag_SO12,
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#endif /* DMAMUX_CSR_SOF12 */
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#if defined(DMAMUX_CSR_SOF13)
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LL_DMAMUX_ClearFlag_SO13,
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#endif /* DMAMUX_CSR_SOF13 */
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#if defined(DMAMUX_CSR_SOF14)
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LL_DMAMUX_ClearFlag_SO14,
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#endif /* DMAMUX_CSR_SOF145 */
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#if defined(DMAMUX_CSR_SOF15)
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LL_DMAMUX_ClearFlag_SO15,
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#endif /* DMAMUX_CSR_SOF15 */
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};
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2020-05-28 00:26:57 +08:00
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uint32_t (*func_ll_is_active_rgo[])(DMAMUX_Channel_TypeDef *DMAMUXx) = {
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2020-04-23 17:38:06 +08:00
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LL_DMAMUX_IsActiveFlag_RGO0,
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LL_DMAMUX_IsActiveFlag_RGO1,
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LL_DMAMUX_IsActiveFlag_RGO2,
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LL_DMAMUX_IsActiveFlag_RGO3,
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};
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void (*func_ll_clear_rgo[])(DMAMUX_Channel_TypeDef *DMAMUXx) = {
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LL_DMAMUX_ClearFlag_RGO0,
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LL_DMAMUX_ClearFlag_RGO1,
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LL_DMAMUX_ClearFlag_RGO2,
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LL_DMAMUX_ClearFlag_RGO3,
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};
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#endif /* DMAMUX_STM32_H_*/
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