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zephyr/drivers/gpio/Kconfig.xlnx_ps

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drivers: gpio: Xilinx PS MIO / EMIO GPIO driver Driver implementation for the Xilinx Processor System MIO / EMIO GPIO controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs. The driver is split up into source and header for a parent controller device and source and header for 1..n child GPIO pin bank devices. The parent device driver takes care of IRQ handling, the GPIO pin bank driver provides pin / bank access according to the API defined by the GPIO subsystem. More than one device for this type of GPIO controller is required as it provides access to a number of GPIO pins well in excess of the 32 pins addressable by the current GPIO API (whereever parameters or return values come in the form of a bit mask): - Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks. - ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-02-14 21:22:29 +08:00
#
# Xilinx Processor System MIO / EMIO GPIO controller driver
# configuration options
#
# Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
# SPDX-License-Identifier: Apache-2.0
#
config GPIO_XLNX_PS
bool "Xilinx Processor System MIO / EMIO GPIO controller driver"
drivers: gpio: Update drivers to use devicetree Kconfig symbol Update gpio drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol to expose the driver and enable it by default based on devicetree. We remove 'depend on' Kconfig for symbols that would be implied by the devicetree node existing. Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-21 01:07:47 +08:00
default y
depends on DT_HAS_XLNX_PS_GPIO_ENABLED
drivers: gpio: Xilinx PS MIO / EMIO GPIO driver Driver implementation for the Xilinx Processor System MIO / EMIO GPIO controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs. The driver is split up into source and header for a parent controller device and source and header for 1..n child GPIO pin bank devices. The parent device driver takes care of IRQ handling, the GPIO pin bank driver provides pin / bank access according to the API defined by the GPIO subsystem. More than one device for this type of GPIO controller is required as it provides access to a number of GPIO pins well in excess of the 32 pins addressable by the current GPIO API (whereever parameters or return values come in the form of a bit mask): - Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks. - ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-02-14 21:22:29 +08:00
depends on !QEMU_TARGET
help
Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.