2020-06-13 02:39:34 +08:00
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/*
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2020-11-24 15:57:50 +08:00
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* Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
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2020-06-13 02:39:34 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h7_dualcore.dtsi>
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/ {
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/*
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* The RAM memories placed here can be used by both cores M4/M7
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* For more information see reference manual and datasheet to STM32H745
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*/
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/* system data RAM accessible over over AXI bus */
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sram0: memory@24000000 {
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reg = <0x24000000 DT_SIZE_K(512)>;
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compatible = "mmio-sram";
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};
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/* system data RAM accessible over over AHB bus */
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sram1: memory@30000000 {
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reg = <0x30000000 DT_SIZE_K(288)>;
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compatible = "mmio-sram";
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};
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/* system data RAM accessible over over AHB bus */
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sram4: memory@38000000 {
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reg = <0x38000000 DT_SIZE_K(64)>;
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compatible = "mmio-sram";
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};
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};
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