uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-03 01:06:07 +08:00
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/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_
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2019-05-03 05:22:00 +08:00
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/*
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* Set the device's IRQ (in devicetree, or whatever) to PCIE_IRQ_DETECT
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* if the device doesn't support MSI and we don't/can't know the wired IRQ
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* allocated by the firmware ahead of time. Use of this functionality will
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* generally also require CONFIG_DYNAMIC_INTERRUPTS.
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*/
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#define PCIE_IRQ_DETECT 0xFFFFFFFU
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uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-03 01:06:07 +08:00
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/*
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* We represent a PCI device ID as [31:16] device ID, [15:0] vendor ID. Not
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* coincidentally, this is same representation used in PCI configuration space.
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*/
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#define PCIE_ID_VEND_SHIFT 0U
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#define PCIE_ID_VEND_MASK 0xFFFFU
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#define PCIE_ID_DEV_SHIFT 16U
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#define PCIE_ID_DEV_MASK 0xFFFFU
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#define PCIE_ID(vend, dev) \
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((((vend) & PCIE_ID_VEND_MASK) << PCIE_ID_VEND_SHIFT) | \
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(((dev) & PCIE_ID_DEV_MASK) << PCIE_ID_DEV_SHIFT))
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#define PCIE_ID_TO_VEND(id) (((id) >> PCIE_ID_VEND_SHIFT) & PCIE_ID_VEND_MASK)
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#define PCIE_ID_TO_DEV(id) (((id) >> PCIE_ID_DEV_SHIFT) & PCIE_ID_DEV_MASK)
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#define PCIE_ID_NONE PCIE_ID(0xFFFF, 0xFFFF)
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/*
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* Since our internal representation of bus/device/function is arbitrary,
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* we choose the same format employed in the x86 Configuration Address Port:
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*
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* [23:16] bus number, [15:11] device number, [10:8] function number
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*
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* All other bits must be zero.
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*
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* The x86 (the only arch, at present, that supports PCI) takes advantage
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* of this shared format to avoid unnecessary layers of abstraction.
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*/
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#define PCIE_BDF_BUS_SHIFT 16U
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#define PCIE_BDF_BUS_MASK 0xFFU
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#define PCIE_BDF_DEV_SHIFT 11U
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#define PCIE_BDF_DEV_MASK 0x1FU
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#define PCIE_BDF_FUNC_SHIFT 8U
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#define PCIE_BDF_FUNC_MASK 0x7U
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#define PCIE_BDF(bus, dev, func) \
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((((bus) & PCIE_BDF_BUS_MASK) << PCIE_BDF_BUS_SHIFT) | \
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(((dev) & PCIE_BDF_DEV_MASK) << PCIE_BDF_DEV_SHIFT) | \
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(((func) & PCIE_BDF_FUNC_MASK) << PCIE_BDF_FUNC_SHIFT))
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#define PCIE_BDF_TO_BUS(bdf) (((bdf) >> PCIE_BDF_BUS_SHIFT) & PCIE_BDF_BUS_MASK)
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#define PCIE_BDF_TO_DEV(bdf) (((bdf) >> PCIE_BDF_DEV_SHIFT) & PCIE_BDF_DEV_MASK)
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#define PCIE_BDF_TO_FUNC(bdf) \
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(((bdf) >> PCIE_BDF_FUNC_SHIFT) & PCIE_BDF_FUNC_MASK)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_ */
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