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zephyr/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052

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arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
# Kconfig - i.MX RT1052
#
# Copyright (c) 2017, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_MIMXRT1052
config SOC
string
soc: defconfig: Consistently quote string defaults In preparation for introducing a warning. Unquoted string defaults work through a quirk of Kconfig (undefined symbols get their name as their string value), but look confusing. It's done inconsistently now too. Suggested by Kumar Gala. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 03:19:21 +08:00
default "mimxrt1052"
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
config ARM_DIV
default 1
config AHB_DIV
default 0
config IPG_DIV
default 3
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
config GPIO
Kconfig: Use 'default' instead of 'def_bool' in Kconfig.defconfig files This can help find unused symbols. Those end up without a type if 'default' is used instead of 'def_bool', which generates a warning. Search for "Kconfig.defconfig" in https://docs.zephyrproject.org/latest/application/kconfig-tips.html for a longer explanation. Keep the 'def_bool' for the following symbols, which seem to be deliberately defined only in Kconfig.defconfig files: - ALTERA_AVALON_I2C - ALTERA_AVALON_MSGDMA - ALTERA_AVALON_PIO - ALTERA_AVALON_QSPI - ALTERA_AVALON_SYSID - CLOCK_CONTROL_IMX_CCM - CPU_EM4_DMIPS - CPU_EM4_FPUDA - CPU_EM4_FPUS - FP_FPU_DA - I2C_GECKO Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-11-14 00:15:49 +08:00
default y
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-16 00:28:47 +08:00
if NET_L2_ETHERNET
soc: nxp_imx: rt: fix enet pll initialization config macro name - Update config macro name for enet pll - Update impacted defconfig of RT1052 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 14:01:41 +08:00
config INIT_ENET_PLL
def_bool y
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-16 00:28:47 +08:00
endif # NET_L2_ETHERNET
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
endif # SOC_MIMXRT1052