2021-06-11 15:33:56 +08:00
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/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_ps2_channel
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/**
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* @file
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* @brief Nuvoton NPCX PS/2 driver
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*
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* This file contains the driver of PS/2 buses (channels) which provides the
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2022-02-24 20:00:55 +08:00
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* connection between Zephyr PS/2 API functions and NPCX PS/2 controller driver
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* to support PS/2 transactions.
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*
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*/
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2022-05-06 16:25:46 +08:00
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#include <zephyr/drivers/clock_control.h>
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2022-02-22 11:17:26 +08:00
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#include <zephyr/drivers/pinctrl.h>
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2022-05-06 16:25:46 +08:00
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#include <zephyr/drivers/ps2.h>
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2021-06-11 15:33:56 +08:00
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#include <soc.h>
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2022-05-06 16:25:46 +08:00
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(ps2_npcx_channel, CONFIG_PS2_LOG_LEVEL);
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#include "ps2_npcx_controller.h"
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/* Device config */
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struct ps2_npcx_ch_config {
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/* Indicate the channel's number of the PS/2 channel device */
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uint8_t channel_id;
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const struct device *ps2_ctrl;
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/* pinmux configuration */
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const struct pinctrl_dev_config *pcfg;
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};
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/* PS/2 api functions */
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static int ps2_npcx_ch_configure(const struct device *dev,
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ps2_callback_t callback_isr)
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{
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const struct ps2_npcx_ch_config *const config = dev->config;
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int ret;
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ret = ps2_npcx_ctrl_configure(config->ps2_ctrl, config->channel_id,
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callback_isr);
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2022-07-06 19:34:50 +08:00
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if (ret != 0) {
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return ret;
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}
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2021-06-28 11:20:01 +08:00
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return ps2_npcx_ctrl_enable_interface(config->ps2_ctrl,
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2021-06-11 15:33:56 +08:00
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config->channel_id, 1);
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}
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static int ps2_npcx_ch_write(const struct device *dev, uint8_t value)
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{
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const struct ps2_npcx_ch_config *const config = dev->config;
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return ps2_npcx_ctrl_write(config->ps2_ctrl, config->channel_id, value);
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}
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static int ps2_npcx_ch_enable_interface(const struct device *dev)
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{
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const struct ps2_npcx_ch_config *const config = dev->config;
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2021-06-28 11:20:01 +08:00
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return ps2_npcx_ctrl_enable_interface(config->ps2_ctrl,
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config->channel_id, 1);
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}
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static int ps2_npcx_ch_inhibit_interface(const struct device *dev)
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{
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const struct ps2_npcx_ch_config *const config = dev->config;
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2021-06-28 11:20:01 +08:00
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return ps2_npcx_ctrl_enable_interface(config->ps2_ctrl,
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config->channel_id, 0);
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}
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/* PS/2 driver registration */
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static int ps2_npcx_channel_init(const struct device *dev)
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{
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const struct ps2_npcx_ch_config *const config = dev->config;
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int ret;
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if (!device_is_ready(config->ps2_ctrl)) {
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LOG_ERR("%s device not ready", config->ps2_ctrl->name);
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return -ENODEV;
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}
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2021-06-11 15:33:56 +08:00
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/* Configure pin-mux for PS/2 device */
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("PS2 pinctrl setup failed (%d)", ret);
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return ret;
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}
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2021-06-11 15:33:56 +08:00
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return 0;
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}
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static const struct ps2_driver_api ps2_channel_npcx_driver_api = {
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.config = ps2_npcx_ch_configure,
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.read = NULL,
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.write = ps2_npcx_ch_write,
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.disable_callback = ps2_npcx_ch_inhibit_interface,
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.enable_callback = ps2_npcx_ch_enable_interface,
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};
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/* PS/2 channel initialization macro functions */
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#define NPCX_PS2_CHANNEL_INIT(inst) \
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\
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PINCTRL_DT_INST_DEFINE(inst); \
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\
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static const struct ps2_npcx_ch_config ps2_npcx_ch_cfg_##inst = { \
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.channel_id = DT_INST_PROP(inst, channel), \
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.ps2_ctrl = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, ps2_npcx_channel_init, NULL, NULL, \
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&ps2_npcx_ch_cfg_##inst, POST_KERNEL, \
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CONFIG_PS2_CHANNEL_INIT_PRIORITY, \
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&ps2_channel_npcx_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(NPCX_PS2_CHANNEL_INIT)
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/* PS/2 channel driver must be initialized after PS/2 controller driver */
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BUILD_ASSERT(CONFIG_PS2_CHANNEL_INIT_PRIORITY > CONFIG_PS2_INIT_PRIORITY);
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