232 lines
7.8 KiB
C
232 lines
7.8 KiB
C
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "memc_nxp_flexram.h"
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#include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/util.h>
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#include <errno.h>
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#include <zephyr/irq.h>
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#include "fsl_device_registers.h"
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#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API)
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BUILD_ASSERT(DT_PROP(FLEXRAM_DT_NODE, flexram_has_magic_addr),
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"SOC does not support magic flexram addresses");
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#endif
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#define BANK_SIZE (DT_PROP(FLEXRAM_DT_NODE, flexram_bank_size) * 1024)
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#define NUM_BANKS DT_PROP(FLEXRAM_DT_NODE, flexram_num_ram_banks)
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#define IS_CHILD_RAM_TYPE(node_id, compat) DT_NODE_HAS_COMPAT(node_id, compat)
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#define DOES_RAM_TYPE_EXIST(compat) \
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DT_FOREACH_CHILD_SEP_VARGS(FLEXRAM_DT_NODE, IS_CHILD_RAM_TYPE, (+), compat)
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#if DOES_RAM_TYPE_EXIST(mmio_sram)
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#define FIND_OCRAM_NODE(node_id) \
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COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, mmio_sram), (node_id), ())
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#define OCRAM_DT_NODE DT_FOREACH_CHILD(FLEXRAM_DT_NODE, FIND_OCRAM_NODE)
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#define OCRAM_START (DT_REG_ADDR(OCRAM_DT_NODE))
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#define OCRAM_END (OCRAM_START + DT_REG_SIZE(OCRAM_DT_NODE))
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#endif /* OCRAM */
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#if DOES_RAM_TYPE_EXIST(nxp_imx_dtcm)
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#define FIND_DTCM_NODE(node_id) \
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COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, nxp_imx_dtcm), (node_id), ())
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#define DTCM_DT_NODE DT_FOREACH_CHILD(FLEXRAM_DT_NODE, FIND_DTCM_NODE)
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#define DTCM_START (DT_REG_ADDR(DTCM_DT_NODE))
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#define DTCM_END (DTCM_START + DT_REG_SIZE(DTCM_DT_NODE))
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#endif /* DTCM */
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#if DOES_RAM_TYPE_EXIST(nxp_imx_itcm)
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#define FIND_ITCM_NODE(node_id) \
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COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, nxp_imx_itcm), (node_id), ())
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#define ITCM_DT_NODE DT_FOREACH_CHILD(FLEXRAM_DT_NODE, FIND_ITCM_NODE)
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#define ITCM_START (DT_REG_ADDR(ITCM_DT_NODE))
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#define ITCM_END (ITCM_START + DT_REG_SIZE(ITCM_DT_NODE))
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#endif /* ITCM */
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#ifdef FLEXRAM_RUNTIME_BANKS_USED
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#define PLUS_ONE_BANK(node_id, prop, idx) 1
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#define COUNT_BANKS \
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DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, PLUS_ONE_BANK, (+))
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BUILD_ASSERT(COUNT_BANKS == NUM_BANKS, "wrong number of flexram banks defined");
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#ifdef OCRAM_DT_NODE
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#define ADD_BANK_IF_OCRAM(node_id, prop, idx) \
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COND_CODE_1(IS_EQ(DT_PROP_BY_IDX(node_id, prop, idx), FLEXRAM_OCRAM), \
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(BANK_SIZE), (0))
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#define OCRAM_TOTAL \
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DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, ADD_BANK_IF_OCRAM, (+))
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BUILD_ASSERT((OCRAM_TOTAL) == DT_REG_SIZE(OCRAM_DT_NODE), "OCRAM node size is wrong");
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#endif /* OCRAM */
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#ifdef DTCM_DT_NODE
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#define ADD_BANK_IF_DTCM(node_id, prop, idx) \
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COND_CODE_1(IS_EQ(DT_PROP_BY_IDX(node_id, prop, idx), FLEXRAM_DTCM), \
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(BANK_SIZE), (0))
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#define DTCM_TOTAL \
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DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, ADD_BANK_IF_DTCM, (+))
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BUILD_ASSERT((DTCM_TOTAL) == DT_REG_SIZE(DTCM_DT_NODE), "DTCM node size is wrong");
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#endif /* DTCM */
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#ifdef ITCM_DT_NODE
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#define ADD_BANK_IF_ITCM(node_id, prop, idx) \
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COND_CODE_1(IS_EQ(DT_PROP_BY_IDX(node_id, prop, idx), FLEXRAM_ITCM), \
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(BANK_SIZE), (0))
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#define ITCM_TOTAL \
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DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, ADD_BANK_IF_ITCM, (+))
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BUILD_ASSERT((ITCM_TOTAL) == DT_REG_SIZE(ITCM_DT_NODE), "ITCM node size is wrong");
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#endif /* ITCM */
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#endif /* FLEXRAM_RUNTIME_BANKS_USED */
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static FLEXRAM_Type *const base = (FLEXRAM_Type *) DT_REG_ADDR(FLEXRAM_DT_NODE);
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#ifdef FLEXRAM_INTERRUPTS_USED
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static flexram_callback_t flexram_callback;
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static void *flexram_user_data;
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void memc_flexram_register_callback(flexram_callback_t callback, void *user_data)
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{
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flexram_callback = callback;
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flexram_user_data = user_data;
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}
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static void nxp_flexram_isr(void *arg)
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{
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ARG_UNUSED(arg);
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if (flexram_callback == NULL) {
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return;
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}
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#if defined(CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT)
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if (base->INT_STATUS & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) {
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base->INT_STATUS |= FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK;
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flexram_callback(flexram_ocram_access_error, flexram_user_data);
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}
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if (base->INT_STATUS & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) {
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base->INT_STATUS |= FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK;
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flexram_callback(flexram_dtcm_access_error, flexram_user_data);
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}
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if (base->INT_STATUS & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) {
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base->INT_STATUS |= FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK;
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flexram_callback(flexram_itcm_access_error, flexram_user_data);
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}
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#endif /* CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT */
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#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API)
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if (base->INT_STATUS & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) {
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base->INT_STATUS |= FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK;
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flexram_callback(flexram_ocram_magic_addr, flexram_user_data);
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}
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if (base->INT_STATUS & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) {
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base->INT_STATUS |= FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK;
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flexram_callback(flexram_dtcm_magic_addr, flexram_user_data);
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}
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if (base->INT_STATUS & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) {
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base->INT_STATUS |= FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK;
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flexram_callback(flexram_itcm_magic_addr, flexram_user_data);
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}
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#endif /* CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API */
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}
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#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API)
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int memc_flexram_set_ocram_magic_addr(uint32_t ocram_addr)
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{
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#ifdef OCRAM_DT_NODE
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ocram_addr -= DT_REG_ADDR(OCRAM_DT_NODE);
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if (ocram_addr >= DT_REG_SIZE(OCRAM_DT_NODE)) {
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return -EINVAL;
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}
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base->OCRAM_MAGIC_ADDR &= ~FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK;
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base->OCRAM_MAGIC_ADDR |= FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(ocram_addr);
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base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK;
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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int memc_flexram_set_itcm_magic_addr(uint32_t itcm_addr)
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{
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#ifdef ITCM_DT_NODE
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itcm_addr -= DT_REG_ADDR(ITCM_DT_NODE);
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if (itcm_addr >= DT_REG_SIZE(ITCM_DT_NODE)) {
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return -EINVAL;
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}
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base->ITCM_MAGIC_ADDR &= ~FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK;
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base->ITCM_MAGIC_ADDR |= FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(itcm_addr);
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base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK;
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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int memc_flexram_set_dtcm_magic_addr(uint32_t dtcm_addr)
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{
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#ifdef DTCM_DT_NODE
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dtcm_addr -= DT_REG_ADDR(DTCM_DT_NODE);
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if (dtcm_addr >= DT_REG_SIZE(DTCM_DT_NODE)) {
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return -EINVAL;
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}
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base->DTCM_MAGIC_ADDR &= ~FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK;
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base->DTCM_MAGIC_ADDR |= FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(dtcm_addr);
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base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK;
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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#endif /* CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API */
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#endif /* FLEXRAM_INTERRUPTS_USED */
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static int nxp_flexram_init(void)
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{
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if (DT_PROP(FLEXRAM_DT_NODE, flexram_tcm_read_wait_mode)) {
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base->TCM_CTRL |= FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK;
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}
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if (DT_PROP(FLEXRAM_DT_NODE, flexram_tcm_write_wait_mode)) {
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base->TCM_CTRL |= FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK;
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}
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#if defined(CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT)
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base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK;
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base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK;
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base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK;
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base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK;
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base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK;
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base->INT_STAT_EN |= FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK;
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#endif /* CONFIG_MEMC_NXP_FLEXRAM_ERROR_INTERRUPT */
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#if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API)
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base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK;
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base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK;
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base->INT_SIG_EN |= FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK;
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#endif /* CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API */
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#ifdef FLEXRAM_INTERRUPTS_USED
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IRQ_CONNECT(DT_IRQN(FLEXRAM_DT_NODE), DT_IRQ(FLEXRAM_DT_NODE, priority),
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nxp_flexram_isr, NULL, 0);
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irq_enable(DT_IRQN(FLEXRAM_DT_NODE));
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#endif /* FLEXRAM_INTERRUPTS_USED */
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return 0;
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}
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SYS_INIT(nxp_flexram_init, EARLY, 0);
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