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zephyr/soc/nxp/layerscape/ls1046a/mmu_regions.c

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soc: arm64: add NXP ls1046a support NXP ls1046a is SoC includes the following functions and features: 1. Four 32/64-bit Arm v8 A72 CPUs 2. Cache coherent interconnect (CCI-400) 3. One 32/64-bit DDR4 SDRAM memory controller with ECC 4. Peripheral interfaces include DPAA network, PCIe, USB, SPI, GPIO, UART, SDHC, IFC, LPUART ... Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-04-02 11:12:03 +08:00
/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
soc: arm64: nxp_layerscape: fix soc.h usage <soc.h> has been traditionally been used as a proxy to HAL headers, register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a different purpose depending on the SoC. In some cases it includes HALs, in some others it works as a header sink/proxy (for no good reason), as a register definition when there's no HAL... To make things worse, it is being included in code that is, in theory, non-SoC specific. This patch is part of a series intended to improve the situation by removing <soc.h> usage when not needed, and by eventually removing it. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-01 00:18:46 +08:00
#include <zephyr/arch/arm64/arm_mmu.h>
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 17:11:04 +08:00
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
soc: arm64: add NXP ls1046a support NXP ls1046a is SoC includes the following functions and features: 1. Four 32/64-bit Arm v8 A72 CPUs 2. Cache coherent interconnect (CCI-400) 3. One 32/64-bit DDR4 SDRAM memory controller with ECC 4. Peripheral interfaces include DPAA network, PCIe, USB, SPI, GPIO, UART, SDHC, IFC, LPUART ... Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-04-02 11:12:03 +08:00
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
soc/arm64: Do not allow userspace to directly access peripherals In some arm64 boards, MMU regions are set so userspace can access all peripherals (MT_P_RW_U_RW), including the GIC. This seems like a mistake, which has been copy/pasted in some boards. Change this to no userspace access by default (MT_P_RW_U_NA), like the other boards. Signed-off-by: Henri Xavier <datacomos@huawei.com>
2022-08-04 21:13:18 +08:00
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
soc: arm64: add NXP ls1046a support NXP ls1046a is SoC includes the following functions and features: 1. Four 32/64-bit Arm v8 A72 CPUs 2. Cache coherent interconnect (CCI-400) 3. One 32/64-bit DDR4 SDRAM memory controller with ECC 4. Peripheral interfaces include DPAA network, PCIe, USB, SPI, GPIO, UART, SDHC, IFC, LPUART ... Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-04-02 11:12:03 +08:00
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
soc/arm64: Do not allow userspace to directly access peripherals In some arm64 boards, MMU regions are set so userspace can access all peripherals (MT_P_RW_U_RW), including the GIC. This seems like a mistake, which has been copy/pasted in some boards. Change this to no userspace access by default (MT_P_RW_U_NA), like the other boards. Signed-off-by: Henri Xavier <datacomos@huawei.com>
2022-08-04 21:13:18 +08:00
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
soc: arm64: add NXP ls1046a support NXP ls1046a is SoC includes the following functions and features: 1. Four 32/64-bit Arm v8 A72 CPUs 2. Cache coherent interconnect (CCI-400) 3. One 32/64-bit DDR4 SDRAM memory controller with ECC 4. Peripheral interfaces include DPAA network, PCIe, USB, SPI, GPIO, UART, SDHC, IFC, LPUART ... Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-04-02 11:12:03 +08:00
};
const struct arm_mmu_config mmu_config = {
.num_regions = ARRAY_SIZE(mmu_regions),
.mmu_regions = mmu_regions,
};