66 lines
1.4 KiB
YAML
66 lines
1.4 KiB
YAML
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32U0 Main PLL node binding:
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Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
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an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
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clock in this acceptable range.
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PLL can have up to 3 output clocks and for each output clock, the
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frequency can be computed with the following formulae:
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f(PLL_P) = f(VCO clock) / PLLP --> to ADC
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f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
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f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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The PLL output frequency must not exceed 122 MHz.
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compatible: "st,stm32u0-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div-m:
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type: int
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required: true
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description: |
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Division factor M of the PLL
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input clock divider
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Valid range: 1 - 8
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mul-n:
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type: int
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required: true
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description: |
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PLL frequency multiplication factor N
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Valid range: 4 - 127
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div-p:
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type: int
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description: |
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PLL VCO division factor P
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Valid range: 2 - 32
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div-q:
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type: int
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description: |
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PLL VCO division factor Q
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Valid range: 2 - 8
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div-r:
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type: int
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required: true
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description: |
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PLL VCO division factor R
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Valid range: 2 - 8
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