2019-09-05 21:19:40 +08:00
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/* ST Microelectronics IIS3DHHC accelerometer sensor
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*
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* Copyright (c) 2019 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Datasheet:
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* https://www.st.com/resource/en/datasheet/iis3dhhc.pdf
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*/
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2020-03-27 05:47:47 +08:00
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#define DT_DRV_COMPAT st_iis3dhhc
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2019-09-05 21:19:40 +08:00
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#include <string.h>
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#include "iis3dhhc.h"
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#include <logging/log.h>
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2020-05-07 02:23:07 +08:00
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#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
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2019-09-05 21:19:40 +08:00
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#define IIS3DHHC_SPI_READ (1 << 7)
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2019-10-11 18:40:57 +08:00
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LOG_MODULE_DECLARE(IIS3DHHC, CONFIG_SENSOR_LOG_LEVEL);
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2019-09-05 21:19:40 +08:00
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static struct spi_config iis3dhhc_spi_conf = {
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2020-03-27 05:47:47 +08:00
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.frequency = DT_INST_PROP(0, spi_max_frequency),
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2019-09-05 21:19:40 +08:00
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.operation = (SPI_OP_MODE_MASTER | SPI_MODE_CPOL |
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SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE),
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2020-03-27 05:47:47 +08:00
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.slave = DT_INST_REG_ADDR(0),
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2019-09-05 21:19:40 +08:00
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.cs = NULL,
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};
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2020-05-28 00:26:57 +08:00
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static int iis3dhhc_spi_read(struct iis3dhhc_data *ctx, uint8_t reg,
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uint8_t *data, uint16_t len)
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2019-09-05 21:19:40 +08:00
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{
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struct spi_config *spi_cfg = &iis3dhhc_spi_conf;
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2020-05-28 00:26:57 +08:00
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uint8_t buffer_tx[2] = { reg | IIS3DHHC_SPI_READ, 0 };
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2019-09-05 21:19:40 +08:00
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const struct spi_buf tx_buf = {
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.buf = buffer_tx,
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.len = 2,
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1
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};
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const struct spi_buf rx_buf[2] = {
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{
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.buf = NULL,
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.len = 1,
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},
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{
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.buf = data,
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.len = len,
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}
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};
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const struct spi_buf_set rx = {
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.buffers = rx_buf,
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.count = 2
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};
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if (spi_transceive(ctx->bus, spi_cfg, &tx, &rx)) {
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return -EIO;
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}
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return 0;
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}
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2020-05-28 00:26:57 +08:00
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static int iis3dhhc_spi_write(struct iis3dhhc_data *ctx, uint8_t reg,
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uint8_t *data, uint16_t len)
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2019-09-05 21:19:40 +08:00
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{
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struct spi_config *spi_cfg = &iis3dhhc_spi_conf;
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2020-05-28 00:26:57 +08:00
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uint8_t buffer_tx[1] = { reg & ~IIS3DHHC_SPI_READ };
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2019-09-05 21:19:40 +08:00
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const struct spi_buf tx_buf[2] = {
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{
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.buf = buffer_tx,
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.len = 1,
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},
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{
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.buf = data,
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.len = len,
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}
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};
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const struct spi_buf_set tx = {
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.buffers = tx_buf,
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.count = 2
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};
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if (spi_write(ctx->bus, spi_cfg, &tx)) {
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return -EIO;
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}
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return 0;
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}
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2019-09-25 16:51:12 +08:00
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stmdev_ctx_t iis3dhhc_spi_ctx = {
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.read_reg = (stmdev_read_ptr) iis3dhhc_spi_read,
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.write_reg = (stmdev_write_ptr) iis3dhhc_spi_write,
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2019-09-05 21:19:40 +08:00
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};
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int iis3dhhc_spi_init(struct device *dev)
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{
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2020-05-29 03:23:02 +08:00
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struct iis3dhhc_data *data = dev->data;
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2019-09-05 21:19:40 +08:00
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data->ctx = &iis3dhhc_spi_ctx;
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data->ctx->handle = data;
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2020-03-27 05:47:47 +08:00
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#if DT_INST_SPI_DEV_HAS_CS_GPIOS(0)
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2019-09-05 21:19:40 +08:00
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/* handle SPI CS thru GPIO if it is the case */
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data->cs_ctrl.gpio_dev = device_get_binding(
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2020-03-27 05:47:47 +08:00
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DT_INST_SPI_DEV_CS_GPIOS_LABEL(0));
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2019-09-05 21:19:40 +08:00
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if (!data->cs_ctrl.gpio_dev) {
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LOG_ERR("Unable to get GPIO SPI CS device");
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return -ENODEV;
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}
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2020-03-27 05:47:47 +08:00
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data->cs_ctrl.gpio_pin = DT_INST_SPI_DEV_CS_GPIOS_PIN(0);
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2020-06-18 15:41:31 +08:00
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data->cs_ctrl.gpio_dt_flags = DT_INST_SPI_DEV_CS_GPIOS_FLAGS(0);
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2019-09-05 21:19:40 +08:00
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data->cs_ctrl.delay = 0U;
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iis3dhhc_spi_conf.cs = &data->cs_ctrl;
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LOG_DBG("SPI GPIO CS configured on %s:%u",
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2020-03-27 05:47:47 +08:00
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DT_INST_SPI_DEV_CS_GPIOS_LABEL(0),
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DT_INST_SPI_DEV_CS_GPIOS_PIN(0));
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2019-09-05 21:19:40 +08:00
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#endif
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return 0;
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}
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2020-05-07 02:23:07 +08:00
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#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
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