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zephyr/soc/arm/renesas_rcar/gen3/Kconfig.series

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soc: arm: add Renesas rcar_gen3 series support Most of the Renesas RCar Gen3 based SoC contains a Cortex R7 processor. This processor has access to the same memory mapped devices than the Cortex-A5x cores. - CPU operates upto 800MHz - Can use ram area from 0x40040000 to 0x42000000 - Has 512 interrupts on GIC-400 compliant with Arm GICv2 Add support for r8a77951 as first SoC of this series which is also known as H3 ES2.0 and is present present on different boards such as Salvator and R-Car Starter Kit(H3ulcb). This first SoC definition is just enough to print Hello World in a ram console. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-13 16:38:41 +08:00
# Copyright (c) 2021 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RCAR_GEN3
bool "Renesas RCAR Gen3 Cortex R7"
select ARM
select CPU_CORTEX_R7
soc: renesas_rcar: gen3: enable L1 cache and branch prediction Use CMSIS abstraction to enable L1 cache and branch prediction. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-03-15 23:18:28 +08:00
select PLATFORM_SPECIFIC_INIT
soc: arm: add Renesas rcar_gen3 series support Most of the Renesas RCar Gen3 based SoC contains a Cortex R7 processor. This processor has access to the same memory mapped devices than the Cortex-A5x cores. - CPU operates upto 800MHz - Can use ram area from 0x40040000 to 0x42000000 - Has 512 interrupts on GIC-400 compliant with Arm GICv2 Add support for r8a77951 as first SoC of this series which is also known as H3 ES2.0 and is present present on different boards such as Salvator and R-Car Starter Kit(H3ulcb). This first SoC definition is just enough to print Hello World in a ram console. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-13 16:38:41 +08:00
select GIC_V2
select CPU_HAS_DCLS
select SOC_FAMILY_RCAR
boards: arm: rcar_h3ulcb: add Timer support Enable CMT timer that can be found on H3ULCB board. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-18 17:07:56 +08:00
select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
soc: arm: add Renesas rcar_gen3 series support Most of the Renesas RCar Gen3 based SoC contains a Cortex R7 processor. This processor has access to the same memory mapped devices than the Cortex-A5x cores. - CPU operates upto 800MHz - Can use ram area from 0x40040000 to 0x42000000 - Has 512 interrupts on GIC-400 compliant with Arm GICv2 Add support for r8a77951 as first SoC of this series which is also known as H3 ES2.0 and is present present on different boards such as Salvator and R-Car Starter Kit(H3ulcb). This first SoC definition is just enough to print Hello World in a ram console. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-13 16:38:41 +08:00
help
Enable support for Renesas RCar Gen3 SoC series