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zephyr/drivers/espi/Kconfig.npcx

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drivers: eSPI: add eSPI driver support for NPCX7 series. In npcx7 series, all of them support the Intel Enhanced Serial Peripheral Interface (eSPI) Revision 1.0. This specification provides a path for migrating host sub-devices via LPC to a lower pin count, higher bandwidth bus. In addition to Host communication via the peripheral channel, it provides virtual wires support, out-of-band communication, and device mastering option over the Chipset SPI flash. Becisdes introducing eSPI device in npcx7, this CL also includes: 1. Add eSPI device tree declarations. 2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI Virtual-Wire signals, eSPI registers, and wake-up input sources. 3. Zephyr eSPI api implementation. 4, Add OOB (Out of Band tunneled SMBus) support. 5. Add configuration files for eSPI test suites. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-10 17:39:44 +08:00
# NPCX eSPI driver configuration options
# Copyright (c) 2020 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
config ESPI_NPCX
driver: npcx7: fixed typo in Kconfig.npcx files. Fixed typo in Kconfig.npcx files. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2020-12-07 13:45:26 +08:00
bool "Nuvoton NPCX embedded controller (EC) ESPI driver"
drivers: eSPI: add eSPI driver support for NPCX7 series. In npcx7 series, all of them support the Intel Enhanced Serial Peripheral Interface (eSPI) Revision 1.0. This specification provides a path for migrating host sub-devices via LPC to a lower pin count, higher bandwidth bus. In addition to Host communication via the peripheral channel, it provides virtual wires support, out-of-band communication, and device mastering option over the Chipset SPI flash. Becisdes introducing eSPI device in npcx7, this CL also includes: 1. Add eSPI device tree declarations. 2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI Virtual-Wire signals, eSPI registers, and wake-up input sources. 3. Zephyr eSPI api implementation. 4, Add OOB (Out of Band tunneled SMBus) support. 5. Add configuration files for eSPI test suites. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-10 17:39:44 +08:00
depends on SOC_FAMILY_NPCX
help
This option enables the Intel Enhanced Serial Peripheral Interface
(eSPI) for NPCX family of processors.
driver: espi: add acpi and customized op codes for lpc r/w request func. This CL introduces two kinds of op codes for espi_api_lpc_read_request and espi_api_lpc_write_request Zephyr espi api functions. One is for supporting ACPI and shared memory region to access ACPI data. The other is customized for certain platforms such as Chromebook and so on. This CL also introduced the following configurations to add the flexibility of these settings. 1. ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM: Host I/O peripheral port number for shared memory region. The default value is default 0x0900 2. ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE: Host I/O peripheral port size for shared memory in npcx series. Please notice the valid value in npcx ec series for this option is 8/16/32/64/128/256/512/1024/2048/4096 bytes. The default value is 256 bytes. This CL also turn off hardware-wire feature which generates VW events that connected to hardware signals such as SMI and SCI. We will set VW output events directly via espi_api_send_vwire() api function. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2020-12-10 13:28:48 +08:00
config ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE
int "Host I/O peripheral port size for shared memory in npcx series"
depends on ESPI_NPCX || ESPI_PERIPHERAL_ACPI_SHM_REGION
default 256
help
This is the port size used by the Host and EC to communicate over
the shared memory region to return the ACPI response data. Please
notice the valid value in npcx ec series for this option is 8/16/32/
64/128/256/512/1024/2048/4096 bytes.
driver: espi: add notification and opcodes for ec host command support. This CL add a new notification event, ESPI_PERIPHERAL_EC_HOST_CMD, and two response opcodes, ECUSTOM_HOST_CMD_GET_PARAM_MEMORY and ECUSTOM_HOST_CMD_SEND_RESULT, to connect with host command sub-system between host and ec. It also introduced three configurations to increase the flexibility of ec host command settings: 1. ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM: Host I/O peripheral port number for ec host command data. The default value is 0x0200. 2. ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM: Host I/O peripheral port number for ec host command parameters. The default value is 0x0800. 3. ESPI_NPCX_PERIPHERAL_HOST_CMD_PARAM_SIZE: Host I/O peripheral port size for ec host command in npcx series. The valid value in npcx ec series for this option is 8/16/32/64/128/256/512/1024/2048/4096 bytes. The default value is 256 bytes. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2020-12-11 13:27:55 +08:00
config ESPI_NPCX_PERIPHERAL_HOST_CMD_PARAM_SIZE
int "Host I/O peripheral port size for ec host command in npcx series"
depends on ESPI_NPCX || ESPI_PERIPHERAL_EC_HOST_CMD
default 256
help
This is the port size used by the Host and EC to communicate over
the shared memory region to return the host command parameter data.
Please notice the valid value in npcx ec series for this option is
8/16/32/64/128/256/512/1024/2048/4096 bytes.
driver: eSPI: npcx: workaround the errata rev1_2, No.3.10 Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel, etc.) during an eSPI transaction might (with low probability) cause the eSPI_SIF module to transition to a wrong state and therefore response with FATAL_ERROR on an incoming transaction. This CL workarounds this issue by clearing the bit 4 of NPCX eSPI specific register#2. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-04-27 16:42:37 +08:00
config ESPI_NPCX_BYPASS_CH_ENABLE_FATAL_ERROR
bool
depends on SOC_SERIES_NPCX7 || SOC_SERIES_NPCX9
default y
help
Workaround the issue documented in NPCX99nF errata rev1_2, No.3.10.
Enabling an eSPI channel during an eSPI transaction might
(with low probability) cause the eSPI_SIF module to transition to
a wrong state and therefore response with FATAL_ERROR on an incoming
transaction.
driver: eSPI: npcx: support multiple bytes mode for Port80 eSPI PUT_IOWR_SHORT protocol can send 1/2/4 bytes of data in a single transaction. This allows the host to send max 32-bits Port80 code at one time. This CL sets bits OFS0_SEL~OFS3_SEL in the DPAR1 register to let the EC hardware put the full Port80 code to DP80BUF FIFO. It also groups the N-byte code into a single 32-bits variable when necessary by analyzing the offset field in the DP80BUF register. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-10-14 15:45:03 +08:00
config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_MULTI_BYTE
bool "Host can write 1/2/4 bytes of Port80 data in a eSPI transaction"
depends on SOC_SERIES_NPCX9 && ESPI_PERIPHERAL_DEBUG_PORT_80
help
EC can accept 1/2/4 bytes of Port 80 data written from the Host in an
eSPI transaction.
driver: Port80: npcx: defer Port80 code sending to workqueue thread If the host sends Port80 postcodes frequently while EC is busy handling other tasks, the Port80 FIFO (16-byte depth) might overflow easily, especially when the host sends the postcode with the 4-byte format. This change defers the handling and sending (to the upper layer) postcodes to the system workqueue thread. It can reduce a lot of (but not all) the overflow case. Also in practice, we usually care about the latest postcodes. The older codes are not significant to the developer. This commit also lowers the printing of the overflow warning to LOG_DEBUG. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-12-06 14:06:24 +08:00
config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_RING_BUF_SIZE
int "Debug Port80 ring buffer size"
depends on ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_MULTI_BYTE
default 256
help
The size of the ring buffer in byte used by the Port80 ISR to store
Postcodes from Host.
drivers: eSPI: add eSPI driver support for NPCX7 series. In npcx7 series, all of them support the Intel Enhanced Serial Peripheral Interface (eSPI) Revision 1.0. This specification provides a path for migrating host sub-devices via LPC to a lower pin count, higher bandwidth bus. In addition to Host communication via the peripheral channel, it provides virtual wires support, out-of-band communication, and device mastering option over the Chipset SPI flash. Becisdes introducing eSPI device in npcx7, this CL also includes: 1. Add eSPI device tree declarations. 2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI Virtual-Wire signals, eSPI registers, and wake-up input sources. 3. Zephyr eSPI api implementation. 4, Add OOB (Out of Band tunneled SMBus) support. 5. Add configuration files for eSPI test suites. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-10 17:39:44 +08:00
# The default value 'y' for the existing options if ESPI_NPCX is selected.
if ESPI_NPCX
config ESPI_OOB_CHANNEL
default y
config ESPI_PERIPHERAL_8042_KBC
default y
config ESPI_PERIPHERAL_HOST_IO
default y
config ESPI_PERIPHERAL_DEBUG_PORT_80
default y
driver: espi: add acpi and customized op codes for lpc r/w request func. This CL introduces two kinds of op codes for espi_api_lpc_read_request and espi_api_lpc_write_request Zephyr espi api functions. One is for supporting ACPI and shared memory region to access ACPI data. The other is customized for certain platforms such as Chromebook and so on. This CL also introduced the following configurations to add the flexibility of these settings. 1. ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM: Host I/O peripheral port number for shared memory region. The default value is default 0x0900 2. ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE: Host I/O peripheral port size for shared memory in npcx series. Please notice the valid value in npcx ec series for this option is 8/16/32/64/128/256/512/1024/2048/4096 bytes. The default value is 256 bytes. This CL also turn off hardware-wire feature which generates VW events that connected to hardware signals such as SMI and SCI. We will set VW output events directly via espi_api_send_vwire() api function. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2020-12-10 13:28:48 +08:00
config ESPI_PERIPHERAL_EC_HOST_CMD
default y
config ESPI_PERIPHERAL_ACPI_SHM_REGION
default y
config ESPI_PERIPHERAL_CUSTOM_OPCODE
default y
drivers: eSPI: add eSPI driver support for NPCX7 series. In npcx7 series, all of them support the Intel Enhanced Serial Peripheral Interface (eSPI) Revision 1.0. This specification provides a path for migrating host sub-devices via LPC to a lower pin count, higher bandwidth bus. In addition to Host communication via the peripheral channel, it provides virtual wires support, out-of-band communication, and device mastering option over the Chipset SPI flash. Becisdes introducing eSPI device in npcx7, this CL also includes: 1. Add eSPI device tree declarations. 2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI Virtual-Wire signals, eSPI registers, and wake-up input sources. 3. Zephyr eSPI api implementation. 4, Add OOB (Out of Band tunneled SMBus) support. 5. Add configuration files for eSPI test suites. Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-10 17:39:44 +08:00
endif #ESPI_NPCX