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zephyr/soc/riscv32/openisa_rv32m1/Kconfig.soc

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soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
# Copyright (c) 2018 Foundries.io Ltd
#
# SPDX-License-Identifier: Apache-2.0
config SOC_OPENISA_RV32M1_RISCV32
bool "OpenISA RV32M1 RISC-V cores"
depends on RISCV32
# The following depends is due to limitations in the linker script.
# It's not inherent to the chip itself.
depends on !CUSTOM_RODATA_LD && !CUSTOM_RWDATA_LD
# The following select is also due to limitations in the linker script.
# (We can't make it a 'depends on' without causing a dependency loop).
select XIP
select HAS_DTS
select ATOMIC_OPERATIONS_C
select VEGA_SDK_HAL
select RISCV_SOC_INTERRUPT_INIT
clock_control: RV32M1: introduce PCC driver / DT bindings Add a Peripheral Clock Controller (PCC) driver. This gates and ungates clocks to various peripherals on the SoC. Signed-off-by: Michael Scott <mike@foundries.io> Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-11-08 02:13:52 +08:00
select CLOCK_CONTROL
soc: riscv32: add RV32M1 SoC as openisa_rv32m1 The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-25 17:40:57 +08:00
help
Enable support for OpenISA RV32M1 RISC-V processors. Choose
this option to target the RI5CY or ZERO-RISCY core. This
option should not be used to target either Arm core.