206 lines
6.5 KiB
C
206 lines
6.5 KiB
C
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/*
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* Copyright (c) 2024, Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SUBSYS_FPGA_BRIDGE_INTEL_H_
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#define ZEPHYR_SUBSYS_FPGA_BRIDGE_INTEL_H_
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#include <zephyr/kernel.h>
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/* Mask for FPGA-HPS bridges */
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#define BRIDGE_MASK 0x0F
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/* Mailbox command header index */
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#define MBOX_CMD_HEADER_INDEX 0x00
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/* Mailbox command memory size */
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#define FPGA_MB_CMD_ADDR_MEM_SIZE 20
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/* Mailbox command response memory size */
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#define FPGA_MB_RESPONSE_MEM_SIZE 20
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/* Config status response length */
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#define FPGA_CONFIG_STATUS_RESPONSE_LEN 0x07
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#define MBOX_CMD_CODE_OFFSET 0x00
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#define MBOX_CMD_ID_MASK 0x7FF
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#define MBOX_CMD_MODE_OFFSET 0x0B
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#define MBOX_CMD_MODE_MASK 0x800
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#define MBOX_DATA_LEN_OFFSET 0x0C
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#define MBOX_DATA_LEN_MASK 0xFFF000
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#define RECONFIG_DIRECT_COUNT_OFFSET 0x00
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#define RECONFIG_DIRECT_COUNT_MASK 0xFF
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#define RECONFIG_INDIRECT_ARG_OFFSET 0x08
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#define RECONFIG_INDIRECT_COUNT_MASK 0xFF00
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#define RECONFIG_INDIRECT_RESPONSE_OFFSET 0x10
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#define RECONFIG_RESPONSE_COUNT_MASK 0xFF0000
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#define RECONFIG_DATA_MB_CMD_SIZE 0x10
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#define RECONFIG_DATA_MB_CMD_INDIRECT_MODE 0x01
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#define RECONFIG_DATA_MB_CMD_LENGTH 0x03
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#define RECONFIG_DATA_MB_CMD_DIRECT_COUNT 0x00
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#define RECONFIG_DATA_MB_CMD_INDIRECT_ARG 0x01
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#define RECONFIG_DATA_MB_CMD_INDIRECT_RESPONSE 0x00
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#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000
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#define RECONFIG_STATUS_RETRY_COUNT 20
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#define MBOX_CONFIG_STATUS_STATE_CONFIG 0x10000000
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#define MBOX_CFGSTAT_VAB_BS_PREAUTH 0x20000000
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#define FPGA_NOT_CONFIGURED_ERROR 0x02000004
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#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xF0000005
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#define RECONFIG_SOFTFUNC_STATUS_CONF_DONE BIT(0)
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#define RECONFIG_SOFTFUNC_STATUS_INIT_DONE BIT(1)
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#define RECONFIG_SOFTFUNC_STATUS_SEU_ERROR BIT(3)
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#define RECONFIG_PIN_STATUS_NSTATUS BIT(31)
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#define MBOX_REQUEST_HEADER(cmd_id, cmd_mode, len) \
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((cmd_id << MBOX_CMD_CODE_OFFSET) & (MBOX_CMD_ID_MASK)) | \
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((cmd_mode << MBOX_CMD_MODE_OFFSET) & (MBOX_CMD_MODE_MASK)) | \
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((len << MBOX_DATA_LEN_OFFSET) & (MBOX_DATA_LEN_MASK))
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#define MBOX_RECONFIG_REQUEST_DATA_FORMAT(direct_count, indirect_arg_count, response_arg_count) \
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((direct_count << RECONFIG_DIRECT_COUNT_OFFSET) & (RECONFIG_DIRECT_COUNT_MASK)) | \
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((indirect_arg_count << RECONFIG_INDIRECT_ARG_OFFSET) & \
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(RECONFIG_INDIRECT_COUNT_MASK)) | \
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((response_arg_count << RECONFIG_INDIRECT_RESPONSE_OFFSET) & \
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(RECONFIG_RESPONSE_COUNT_MASK))
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union mailbox_response_header {
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/* Header of the config status response */
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uint32_t header;
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struct {
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/* error_code – Field provides a basic description of whether the command
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* succeeded or not. A successful response returns an error code of 0x0,
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* non-zero values indicate failure
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*/
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uint32_t error_code : 11;
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/* indirect_bit - Field indicates an indirect command */
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uint32_t indirect_bit : 1;
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/* data_length - Field counts the number of word arguments which follow the
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* response header word. The meaning of these words depends on the command
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* code. Units are words
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*/
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uint32_t data_length : 11;
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/* reserve bit */
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uint32_t reserved_bit : 1;
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/* id - Field is returned unchanged from the matching command header and is
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* useful for matching responses to commands along with the CLIENT
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*/
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uint32_t id : 4;
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/* client_id - Field is returned unchanged from the matching command header and
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* is useful for matching responses to commands along with the ID
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*/
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uint32_t client_id : 4;
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} mailbox_resp_header;
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};
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union config_status_version {
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/* Version of the config status response */
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uint32_t version;
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struct {
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/* update number bits */
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uint32_t update_number : 8;
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/* minor acds release number bits */
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uint32_t minor_acds_release_number : 8;
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/* major acds release number bits */
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uint32_t major_acds_release_number : 8;
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/* qspi flash index bits */
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uint32_t qspi_flash_index : 8;
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} response_version_member;
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};
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union config_status_pin_status {
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uint32_t pin_status;
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struct {
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/* msel bits */
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uint32_t msel : 4;
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/* pmf data bits */
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uint32_t pmf_data : 4;
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/* reserve bits */
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uint32_t reserved_bit : 22;
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/* nconfig bits */
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uint32_t nconfig : 1;
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/* nconfig_status bits */
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uint32_t nconfig_status : 1;
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} pin_status_member;
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};
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/* Struct to store the fpga_config_status */
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struct fpga_config_status {
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/* Response header */
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union mailbox_response_header header;
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/* Config state idle or config mode */
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uint32_t state;
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/* Version number */
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union config_status_version version;
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/* Pin status */
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union config_status_pin_status pin_status;
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/* Soft function status details */
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uint32_t soft_function_status;
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/* Location in the bitstream where the error occurred */
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uint32_t error_location;
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/* Data is non-zero only for certain errors. The contents are highly dependent
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* on which error was reported. The meaning of this data will not be made available to
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* customers and can only be interpreted by investigating the source code directly
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*/
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uint32_t error_details;
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};
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enum smc_cmd_code {
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/* SMC COMMAND ID to disable all the bridges */
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FPGA_ALL_BRIDGE_DISABLE = 0x00,
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/* SMC COMMAND ID to enable all the bridges */
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FPGA_ALL_BRIDGE_ENABLE = 0x01,
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/* SMC Cancel Command */
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FPGA_CANCEL = 0x03,
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/* SMC COMMAND ID to check Reconfig status to SDM via mailbox */
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FPGA_CONFIG_STATUS = 0x04,
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/* SMC COMMAND ID to check Reconfig status to SDM via mailbox */
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FPGA_RECONFIG_STATUS = 0x09
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};
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enum mbox_reconfig_status_resp {
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/* Mailbox reconfig status header */
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MBOX_RECONFIG_STATUS_HEADER,
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/* Mailbox reconfig status state */
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MBOX_RECONFIG_STATUS_STATE,
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/* Mailbox reconfig status version */
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MBOX_RECONFIG_STATUS_VERSION,
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/* Mailbox reconfig status pin status */
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MBOX_RECONFIG_STATUS_PIN_STATUS,
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/* Mailbox reconfig status soft function */
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MBOX_RECONFIG_STATUS_SOFT_FUNCTION,
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/* Mailbox reconfig status error location */
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MBOX_RECONFIG_STATUS_ERROR_LOCATION,
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/* Mailbox reconfig status error details */
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MBOX_RECONFIG_STATUS_ERROR_DETAILS
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};
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enum smc_request {
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/* SMC request parameter a2 index*/
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SMC_REQUEST_A2_INDEX = 0x00,
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/* SMC request parameter a3 index */
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SMC_REQUEST_A3_INDEX = 0x01
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};
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/* SIP SVC response private data */
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struct sip_svc_private_data {
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struct sip_svc_response response;
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uint32_t *mbox_response_data;
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uint32_t mbox_response_len;
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struct k_sem smc_sem;
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struct fpga_config_status config_status;
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};
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#endif
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