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zephyr/boards/x86/acrn/acrn.yaml

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boards/x86: add ACRN UOS sample board configuration Based on prior work by @dcpleung. It's suboptimal, but it provides a working starting point for ACRN work. The x86 board/SoC abstractions really need to be refactored to make this "board" (and other x86-based "boards", both extant and future) cleaner and easier to maintain. Punt. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-03-15 00:49:56 +08:00
identifier: acrn
name: ACRN
type: mcu
arch: x86
toolchain:
- zephyr
ram: 8192
x86: fix XIP SOC support and defaults XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-10 15:41:08 +08:00