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zephyr/dts/arm/xilinx/zynqmp_rpu.dtsi

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dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately. ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and Cortex-A for APU. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within one project, the RPU and APU should be considered separate platforms. This commit relocates the device tree nodes that are not common between RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi). When Cortex-A53 APU support is added in the future, an additional dtsi file (zynqmp_apu.dtsi) for specifying the APU device tree should be added. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-31 21:40:06 +08:00
/*
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/xilinx/zynqmp.dtsi>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
dts: xilinx_zynqmp: Fix incorrect RPU device tree specification. This commit fixes the following problems with the RPU device tree: 1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not Cortex-R4. 2. RPU and APU use different interrupt controllers (PL390 GICv1 and GIC-400 GICv2, respectively) mapped to the same CPU local bus address region but with different offsets for the distributor and CPU interrupt control register sets. The GIC address mapping specified by the current dts is that of an APU and does not apply to the PL390 GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register Reference" document from Xilinx for more information). For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-31 21:50:21 +08:00
compatible = "arm,cortex-r5f";
dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately. ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and Cortex-A for APU. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within one project, the RPU and APU should be considered separate platforms. This commit relocates the device tree nodes that are not common between RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi). When Cortex-A53 APU support is added in the future, an additional dtsi file (zynqmp_apu.dtsi) for specifying the APU device tree should be added. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-31 21:40:06 +08:00
reg = <0>;
};
};
soc {
interrupt-parent = <&gic>;
dts: xilinx_zynqmp: Fix incorrect RPU device tree specification. This commit fixes the following problems with the RPU device tree: 1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not Cortex-R4. 2. RPU and APU use different interrupt controllers (PL390 GICv1 and GIC-400 GICv2, respectively) mapped to the same CPU local bus address region but with different offsets for the distributor and CPU interrupt control register sets. The GIC address mapping specified by the current dts is that of an APU and does not apply to the PL390 GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register Reference" document from Xilinx for more information). For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-31 21:50:21 +08:00
gic: interrupt-controller@f9000000 {
dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately. ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and Cortex-A for APU. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within one project, the RPU and APU should be considered separate platforms. This commit relocates the device tree nodes that are not common between RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi). When Cortex-A53 APU support is added in the future, an additional dtsi file (zynqmp_apu.dtsi) for specifying the APU device tree should be added. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-31 21:40:06 +08:00
compatible = "arm,gic";
dts: xilinx_zynqmp: Fix incorrect RPU device tree specification. This commit fixes the following problems with the RPU device tree: 1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not Cortex-R4. 2. RPU and APU use different interrupt controllers (PL390 GICv1 and GIC-400 GICv2, respectively) mapped to the same CPU local bus address region but with different offsets for the distributor and CPU interrupt control register sets. The GIC address mapping specified by the current dts is that of an APU and does not apply to the PL390 GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register Reference" document from Xilinx for more information). For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-31 21:50:21 +08:00
reg = <0xf9000000 0x1000>,
<0xf9001000 0x100>;
dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately. ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and Cortex-A for APU. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within one project, the RPU and APU should be considered separate platforms. This commit relocates the device tree nodes that are not common between RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi). When Cortex-A53 APU support is added in the future, an additional dtsi file (zynqmp_apu.dtsi) for specifying the APU device tree should be added. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-31 21:40:06 +08:00
interrupt-controller;
#interrupt-cells = <4>;
label = "GIC";
status = "okay";
};
};
};