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zephyr/drivers/interrupt_controller/Kconfig

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kconfig: Clean up header comments and make them consistent Use this short header style in all Kconfig files: # <description> # <copyright> # <license> ... Also change all <description>s from # Kconfig[.extension] - Foo-related options to just # Foo-related options It's clear enough that it's about Kconfig. The <description> cleanup was done with this command, along with some manual cleanup (big letter at the start, etc.) git ls-files '*Kconfig*' | \ xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /' Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-01 20:45:29 +08:00
# interrupt controller configuration options
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
# Copyright (c) 2015 Intel Corporation
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
# SPDX-License-Identifier: Apache-2.0
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
menu "Interrupt Controllers"
arc: move interrupt controller to drivers/ Change-Id: I731c99062f4b5d2d4d1eb6a3c546ed5f3e494fa4 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-06-20 21:26:06 +08:00
config ARCV2_INTERRUPT_UNIT
bool "ARCv2 Interrupt Unit"
default y
depends on ARC
help
kconfig: fix help syntax and add spaces Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-13 23:08:21 +08:00
The ARCv2 interrupt unit has 16 allocated exceptions associated with
vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
The interrupt unit is optional in the ARCv2-based processors. When
building a processor, you can configure the processor to include an
interrupt unit. The ARCv2 interrupt unit is highly programmable.
interupt_controller/stm32_exti: driver for STM32 EXTI controller Introcuce a driver for External Interrupt/Event Controller (EXTI) found on STM32 MCUs. Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-14 23:29:46 +08:00
riscv32: riscv-privilege: integrate common code This commit moves code from fe310 platform into RISC-V privilege common folder. This way the code can be reused by other platforms in future. signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-11 01:02:14 +08:00
config PLIC
bool "Platform Level Interrupt Controller (PLIC)"
interrupt_controller: added support for the SiFive Freedom E310 PLIC driver The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows the riscv PLIC specification as defined in the riscv privilege architecture specification. It provides implementation for the riscv PLIC APIs as required by the riscv-privilege SOC Family for SOCs providing support for the RISCV_HAS_PLIC config. Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:16:30 +08:00
default y
qemu_riscv32: use hifive1 configuration Use hifive1 configuration for this qemu and set SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000 Fixes #10043 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 22:37:38 +08:00
depends on SOC_FAMILY_RISCV_PRIVILEGE
interrupt_controller: added support for the SiFive Freedom E310 PLIC driver The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows the riscv PLIC specification as defined in the riscv privilege architecture specification. It provides implementation for the riscv PLIC APIs as required by the riscv-privilege SOC Family for SOCs providing support for the RISCV_HAS_PLIC config. Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:16:30 +08:00
select RISCV_HAS_PLIC
interrupt: Convert RISC-V plic to use multi-level irq support Utilize the multi-level irq infrastructure and replace custom handling for PLIC on riscv-privilege SoCs. The old code offset IRQs in drivers and various places with RISCV_MAX_GENERIC_IRQ. Instead utilize Zephyr's encoded IRQ and replace offsets in drivers with the IRQ define from DTS. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 12:01:37 +08:00
select MULTI_LEVEL_INTERRUPTS
select 2ND_LEVEL_INTERRUPTS
interrupt_controller: added support for the SiFive Freedom E310 PLIC driver The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows the riscv PLIC specification as defined in the riscv privilege architecture specification. It provides implementation for the riscv PLIC APIs as required by the riscv-privilege SOC Family for SOCs providing support for the RISCV_HAS_PLIC config. Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:16:30 +08:00
help
riscv32: riscv-privilege: integrate common code This commit moves code from fe310 platform into RISC-V privilege common folder. This way the code can be reused by other platforms in future. signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-11 01:02:14 +08:00
Platform Level Interrupt Controller provides support
for external interrupt lines defined by the RISC-V SoC;
interrupt_controller: added support for the SiFive Freedom E310 PLIC driver The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows the riscv PLIC specification as defined in the riscv privilege architecture specification. It provides implementation for the riscv PLIC APIs as required by the riscv-privilege SOC Family for SOCs providing support for the RISCV_HAS_PLIC config. Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:16:30 +08:00
drivers: interrupt_controller: Add SweRV PIC support Add support for the built-in Programmable Interrupt Controller found in the SweRV EH1 RISC-V CPU Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
2019-10-10 19:51:18 +08:00
config SWERV_PIC
bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
default n
help
Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU;
drivers: interrupt_controller: add LiteX interrupt controller driver Add LiteX interrupt controller driver and bindings for this device. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-03-28 21:44:12 +08:00
config VEXRISCV_LITEX_IRQ
bool "VexRiscv LiteX Interrupt controller"
depends on SOC_RISCV32_LITEX_VEXRISCV
help
IRQ implementation for LiteX VexRiscv
interrupt_controller: gic: Add support for the GIC400 The GIC400 is a common interrupt controller that can be used with the Cortex A and R series processors. This patch adds basic interrupt handling for the GIC, but does not handle multiple routing or priorities. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2018-04-18 17:13:06 +08:00
config GIC
bool "ARM Generic Interrupt Controller (GIC)"
depends on CPU_CORTEX_R
help
The ARM Generic Interrupt Controller works with Cortex-A and
Cortex-R processors.
drivers/interrupt_controller: Introduce multi-level interrupt support In a scenario where a platform harbours multiple interrupts to the extent the core cannot support it, an interrupt controller is added as an additional level of interrupt. It typically combines several sources of interrupt into one line that is then routed to the parent controller. Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2017-12-24 17:48:57 +08:00
source "drivers/interrupt_controller/Kconfig.multilevel"
drivers/interrupt_controller: Split Kconfig for clarity Let's move loapic and dw related options into there own Kconfig file. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-12-18 16:42:14 +08:00
source "drivers/interrupt_controller/Kconfig.loapic"
source "drivers/interrupt_controller/Kconfig.dw"
source "drivers/interrupt_controller/Kconfig.stm32"
drivers/interrupt_controller: Renaming s1000 to cavs If it is such a thing (a CAVT intc), it will not be targeting Intel s1000 SoC only. UP squarde ADSP use the same intc. So renaming it to CAVS. Though CAVS name might be wrong (CAVS being an overall architecture name, and not an IP block specification). Reducing the amount of lines by using if/endif as well. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-12-18 16:48:56 +08:00
source "drivers/interrupt_controller/Kconfig.cavs"
drivers: interrupts: introduce CAVS interrupt logic CAVS interrupt logic is an intel IP that combines several sources of interrupt into one line that is then routed to the parent controller. CAVS stands for "connected Audio, Voice and Speech". This IP supports 4 lines which can have a max of 32 interrupts each. Change-Id: Ia6be51428bedf1011d148ae1fc5d4c34252c05da Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-12 01:06:20 +08:00
interrupt_controller: RV32M1: add intmux driver / DT bindings Add a level 2 interrupt controller for the RV32M1 SoC. This uses the INTMUX peripheral. As a first customer, convert the timer driver over to using this, adding nodes for the LPTMR peripherals. This lets users select the timer instance they want to use, and what intmux channel they want to route its interrupt to, using DT overlays. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Mike Scott <mike@foundries.io>
2018-11-25 17:41:38 +08:00
source "drivers/interrupt_controller/Kconfig.rv32m1"
drivers: gpio: sam0: Add interrupt support This adds interrupt support to the SAM0 GPIO driver. This is heavily inspired by @nzmichaelh work in #5715. The primary difference from that implementation is that here the External Interrupt Controller (EIC) is separated out into an interrupt controller driver that is less tightly coupled to the GPIO API. Instead it implements more of a conversion from the EIC's own odd multiplexing to a more traditional port and pin mask IRQ-like callback. Unfortunately, through the EIC on the SAMD2x are relatively well behaved in terms of pin to EIC line mappings, other chips that share the peripheral interface are not. So the EIC driver implements a per-line lookup to the pin and port pair using definitions extracted from the ASF headers. The EIC driver still makes some assumptions about how it will be used: mostly it assumes exactly one callback per port. This should be fine as the only intended user is the GPIO driver itself. This has been tested with some simple programs and with tests/drivers/gpio/gpio_basic_api on a SAMD21 breakout and an adafruit_trinket_m0 board. Signed-off-by: Derek Hageman <hageman@inthat.cloud>
2019-03-02 10:29:07 +08:00
source "drivers/interrupt_controller/Kconfig.sam0"
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
endmenu