92 lines
2.6 KiB
C
92 lines
2.6 KiB
C
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/*
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* Copyright (c) 2020 PHYTEC Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_
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#define ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_
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#define GD7965_CMD_PSR 0x00
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#define GD7965_CMD_PWR 0x01
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#define GD7965_CMD_POF 0x02
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#define GD7965_CMD_PFS 0x03
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#define GD7965_CMD_PON 0x04
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#define GD7965_CMD_PMES 0x05
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#define GD7965_CMD_BTST 0x06
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#define GD7965_CMD_DSLP 0x07
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#define GD7965_CMD_DTM1 0x10
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#define GD7965_CMD_DSP 0x11
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#define GD7965_CMD_DRF 0x12
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#define GD7965_CMD_DTM2 0x13
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#define GD7965_CMD_DUSPI 0x15
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#define GD7965_CMD_AUTO 0x17
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#define GD7965_CMD_LUTOPT 0x2A
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#define GD7965_CMD_KWOPT 0x2B
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#define GD7965_CMD_PLL 0x30
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#define GD7965_CMD_TSC 0x40
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#define GD7965_CMD_TSE 0x41
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#define GD7965_CMD_TSW 0x42
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#define GD7965_CMD_TSR 0x43
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#define GD7965_CMD_PBC 0x44
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#define GD7965_CMD_CDI 0x50
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#define GD7965_CMD_LPD 0x51
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#define GD7965_CMD_EVS 0x52
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#define GD7965_CMD_TCON 0x60
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#define GD7965_CMD_TRES 0x61
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#define GD7965_CMD_GSST 0x65
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#define GD7965_CMD_REV 0x70
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#define GD7965_CMD_FLG 0x71
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#define GD7965_CMD_AMV 0x80
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#define GD7965_CMD_VV 0x81
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#define GD7965_CMD_VDCS 0x82
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#define GD7965_CMD_PTL 0x90
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#define GD7965_CMD_PTIN 0x91
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#define GD7965_CMD_PTOUT 0x92
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#define GD7965_CMD_PGM 0xA0
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#define GD7965_CMD_APG 0xA1
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#define GD7965_CMD_ROTP 0xA2
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#define GD7965_CMD_CCSET 0xE0
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#define GD7965_CMD_PWS 0xE3
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#define GD7965_CMD_LVSEL 0xE4
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#define GD7965_CMD_TSSET 0xE5
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#define GD7965_CMD_TSBDRY 0xE7
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#define GD7965_PSR_REG BIT(5)
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#define GD7965_PSR_KW_R BIT(4)
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#define GD7965_PSR_UD BIT(3)
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#define GD7965_PSR_SHL BIT(2)
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#define GD7965_PSR_SHD BIT(1)
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#define GD7965_PSR_RST BIT(0)
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#define GD7965_AUTO_PON_DRF_POF 0xA5
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#define GD7965_AUTO_PON_DRF_POF_DSLP 0xA7
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#define GD7965_CDI_REG_LENGTH 2U
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#define GD7965_CDI_BDZ_DDX_IDX 0
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#define GD7965_CDI_CDI_IDX 1
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#define GD7965_CDI_BDZ BIT(7)
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#define GD7965_CDI_BDV1 BIT(5)
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#define GD7965_CDI_BDV0 BIT(4)
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#define GD7965_CDI_N2OCP BIT(3)
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#define GD7965_CDI_DDX1 BIT(1)
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#define GD7965_CDI_DDX0 BIT(0)
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#define GD7965_TRES_REG_LENGTH 4U
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#define GD7965_TRES_HRES_IDX 0
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#define GD7965_TRES_VRES_IDX 2
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#define GD7965_PTL_REG_LENGTH 9U
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#define GD7965_PTL_HRST_IDX 0
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#define GD7965_PTL_HRED_IDX 2
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#define GD7965_PTL_VRST_IDX 4
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#define GD7965_PTL_VRED_IDX 6
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#define GD7965_PTL_PT_SCAN BIT(0)
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/* Time constants in ms */
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#define GD7965_RESET_DELAY 10U
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#define GD7965_PON_DELAY 100U
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#define GD7965_BUSY_DELAY 1U
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#endif /* ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_ */
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