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zephyr/dts/riscv/openisa/rv32m1_zero_riscy.dtsi

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dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
/*
* Copyright 2018 Foundries.io Ltd
* SPDX-License-Identifier: Apache-2.0
*/
dts: riscv: openisa: Move SoC devicetree includes under a vendor dir Cleans up SoC devicetree include file locations to follow the convention of dts/<arch>/<vendor>/ Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-04-30 05:17:02 +08:00
#include <riscv/openisa/rv32m1.dtsi>
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
/ {
aliases {
intmux = &intmux1;
system-lptmr = &lptmr2;
};
cpus {
/delete-node/ cpu@0;
};
};
soc: riscv32: Move rv32m1 flash memory definitions to dts Moves the flash memory definitions from Kconfig to device tree for the rv32m1 ri5cy and zero-riscy cores. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-05-07 02:50:52 +08:00
&m0_flash {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* This configuration assumes the Arm cores are disabled, as
* these base addresses contain the Arm core vector tables if
* they are used.
*/
zero_riscy_code_partition: partition@1000000 {
reg = <0x01000000 0x0003ff00>;
};
zero_riscy_vector_partition: partition@3ff00 {
reg = <0x0003ff00 0x100>;
};
};
};
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
/*
* INTMUX channels below are somewhat arbitrary.
*
* The peripherals are all placed in channel 0. This can be overridden with
* overlays, e.g. to manage IRQ priorities, and it will Just Work, but using
* fewer channels here allows disabling unused ones in Kconfig, making the
* binary smaller.
*
* Each enabled channel requires 256 bytes in _sw_isr_table, so the savings for
* disabling channels can add up.
*/
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
/delete-node/ &intmux0;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
&intmux1 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
status = "okay";
};
&intmux1_ch0 {
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
interrupt-parent = <&event1>;
dts: riscv32: rv32m1: Disable unused interrupt multiplexers Commit 948ef47cf4 ("dts: riscv32: Add rv32m1 zero-riscy core") put common ri5cy and zero_riscy DT parts in rv32m1.dtsi, with two separate rv32m1_ri5cy.dtsi rv32m1_zero_riscy.dtsi files that #include it. The two interrupt multiplexers are defined in the common rv32m1.dtsi file, but rv32m1_ri5cy.dtsi rv32m1_zero_riscy.dtsi each only specify 'interrupts' for one of them. Since 'interrupts' is 'category: required' in openisa,rv32m1-intmux.yaml, this leads to warnings (or errors with the new DT parser). Disable (status = "disabled") the two interrupt multiplexers in the common rv32m1.dtsi file and enable them in the board-specific files to fix it. Required props. are only checked for enabled nodes. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-07-19 23:26:20 +08:00
status = "okay";
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
&intmux1_ch1 {
interrupt-parent = <&event1>;
};
&intmux1_ch2 {
interrupt-parent = <&event1>;
};
&intmux1_ch3 {
interrupt-parent = <&event1>;
};
&intmux1_ch4 {
interrupt-parent = <&event1>;
};
&intmux1_ch5 {
interrupt-parent = <&event1>;
};
&intmux1_ch6 {
interrupt-parent = <&event1>;
};
&intmux1_ch7 {
interrupt-parent = <&event1>;
};
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
&lptmr0 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <6>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
&lptmr1 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <7>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
&lptmr2 {
interrupt-parent = <&event1>;
interrupts = <14>;
};
&gpioa {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <25>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
&gpiob {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <26>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
&gpioc {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <27>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
&gpiod {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <28>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
&gpioe {
interrupt-parent = <&event1>;
interrupts = <21>;
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpuart0 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <21>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpuart1 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <22>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpuart2 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <23>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpuart3 {
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
interrupt-parent = <&event1>;
interrupts = <20>;
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpi2c0 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <13>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpi2c1 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <14>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpi2c2 {
dts: rv32m1: Rework interrupt mux dts descriptions Each intmux block acts like 8 interrupt controllers in which we can have multiple device interrupts on a single channel and that channel than interrupt than chained to another interrupt controller (in the case of the RISC-V cores, it is the event unit). So to describe things better to properly be able to walk the interrupt chain in the device tree we treat each channel in the interrupt mux as an interrupt controller rather than the intmux as a single interrupt controller. In the future this will allow the device tree generation code to walk the interrupt chain from the device and up through any interrupt controllers to generate the IRQ value that Zephyr expects (rather than us hard coding this into the DTS). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:30:08 +08:00
interrupt-parent = <&intmux1_ch0>;
irq: rv32m1: Fixup IRQ values for multi-level IRQ handling Remove the handcoded multi-level IRQ values in device tree. We now are able to generate the encoded multi-level IRQ value. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-09 03:38:34 +08:00
interrupts = <15>;
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpi2c3 {
dts: riscv32: Add rv32m1 zero-riscy core support Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-04-18 04:34:57 +08:00
interrupt-parent = <&event1>;
interrupts = <16>;
};
drivers: spi: rv32m1: Add driver for RV32M1 LPSPI Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC. Based heavily on the existing mcux LPSPI driver. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2019-08-07 23:13:35 +08:00
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpspi0 {
drivers: spi: rv32m1: Add driver for RV32M1 LPSPI Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC. Based heavily on the existing mcux LPSPI driver. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2019-08-07 23:13:35 +08:00
interrupt-parent = <&intmux1_ch0>;
interrupts = <18>;
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpspi1 {
drivers: spi: rv32m1: Add driver for RV32M1 LPSPI Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC. Based heavily on the existing mcux LPSPI driver. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2019-08-07 23:13:35 +08:00
interrupt-parent = <&intmux1_ch0>;
interrupts = <19>;
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpspi2 {
drivers: spi: rv32m1: Add driver for RV32M1 LPSPI Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC. Based heavily on the existing mcux LPSPI driver. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2019-08-07 23:13:35 +08:00
interrupt-parent = <&intmux1_ch0>;
interrupts = <20>;
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&lpspi3 {
drivers: spi: rv32m1: Add driver for RV32M1 LPSPI Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC. Based heavily on the existing mcux LPSPI driver. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2019-08-07 23:13:35 +08:00
interrupt-parent = <&event1>;
interrupts = <19>;
};
dts: riscv: add Generic FSK node The Generic FSK controller enables radio operation using a custom GFSK/GMSK or MSK modulation format achieved by programming a set of PHY variables such as BT product, modulation index and modulation filter co-efficients (such that max frequency deviation <= 500kHz). Generic FSK mode also offers a highly configurable packet structure, variable bit rate transmission and reception, some limited packet (header) processing, and interface to a RAM-based Packet Buffer. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
2019-09-13 22:20:48 +08:00
&generic_fsk {
interrupt-parent = <&intmux1_ch0>;
interrupts = <17>;
};
dts: riscv: rv32m1: add timer/pwm modules Add device tree nodes for the Timer/PWM (TPM) modules present in the OpenISA RV32M1 SoC. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2019-12-04 00:13:24 +08:00
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&tpm0 {
dts: riscv: rv32m1: add timer/pwm modules Add device tree nodes for the Timer/PWM (TPM) modules present in the OpenISA RV32M1 SoC. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2019-12-04 00:13:24 +08:00
interrupt-parent = <&intmux1_ch0>;
interrupts = <8>;
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&tpm1 {
dts: riscv: rv32m1: add timer/pwm modules Add device tree nodes for the Timer/PWM (TPM) modules present in the OpenISA RV32M1 SoC. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2019-12-04 00:13:24 +08:00
interrupt-parent = <&intmux1_ch0>;
interrupts = <9>;
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&tpm2 {
dts: riscv: rv32m1: add timer/pwm modules Add device tree nodes for the Timer/PWM (TPM) modules present in the OpenISA RV32M1 SoC. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2019-12-04 00:13:24 +08:00
interrupt-parent = <&intmux1_ch0>;
interrupts = <10>;
};
soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Also rename various node labels to match the SoC docs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 21:37:21 +08:00
&tpm3 {
dts: riscv: rv32m1: add timer/pwm modules Add device tree nodes for the Timer/PWM (TPM) modules present in the OpenISA RV32M1 SoC. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2019-12-04 00:13:24 +08:00
interrupt-parent = <&event1>;
interrupts = <15>;
};
drivers: entropy: rv32m1_trng: Add DTS support to rv32m1_trng driver Add a YAML, DTS node and driver support to utilize data from devicetree for register address and driver name. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-02 00:10:31 +08:00
&trng {
interrupt-parent = <&event1>;
interrupts = <12>;
};