OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/dts/riscv/gigadevice/gd32vf103Xb.dtsi

17 lines
267 B
Plaintext
Raw Normal View History

soc: riscv: Add initial support for GigaDevice GD32V SoC Add GigaDevice GD32V SoC. GD32V has non-standard CSR. It doesn't use common startup code. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2020-03-03 20:27:10 +08:00
/*
* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <gigadevice/gd32vf103.dtsi>
dts: gigadevice: simplify flash/sram size assignments Make use of nodelabels to extend flash/sram nodes instead of re-defining the whole tree. This pattern is already used in some other files. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-24 05:40:43 +08:00
&sram0 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc: riscv: Add initial support for GigaDevice GD32V SoC Add GigaDevice GD32V SoC. GD32V has non-standard CSR. It doesn't use common startup code. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2020-03-03 20:27:10 +08:00
dts: gigadevice: simplify flash/sram size assignments Make use of nodelabels to extend flash/sram nodes instead of re-defining the whole tree. This pattern is already used in some other files. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-24 05:40:43 +08:00
&flash0 {
reg = <0x08000000 DT_SIZE_K(128)>;
soc: riscv: Add initial support for GigaDevice GD32V SoC Add GigaDevice GD32V SoC. GD32V has non-standard CSR. It doesn't use common startup code. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2020-03-03 20:27:10 +08:00
};