2019-04-06 21:08:09 +08:00
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/* SPDX-License-Identifier: Apache-2.0 */
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2018-02-24 00:07:13 +08:00
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/* SoC level DTS fixup file */
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2018-11-13 22:15:23 +08:00
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#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_3F8_BASE_ADDRESS
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2019-02-26 06:26:03 +08:00
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#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_3F8_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_3F8_LABEL
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2018-11-13 22:15:23 +08:00
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#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_3F8_IRQ_0
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2019-02-26 06:26:03 +08:00
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#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_3F8_IRQ_0_PRIORITY
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2018-11-13 22:15:23 +08:00
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#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_3F8_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_3F8_CLOCK_FREQUENCY
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2018-11-13 19:24:15 +08:00
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2018-11-13 22:15:23 +08:00
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#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_2F8_BASE_ADDRESS
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2019-02-26 06:26:03 +08:00
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#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_2F8_CURRENT_SPEED
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#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_2F8_LABEL
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2018-11-13 22:15:23 +08:00
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#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_2F8_IRQ_0
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2019-02-26 06:26:03 +08:00
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#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_2F8_IRQ_0_PRIORITY
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2018-11-13 22:15:23 +08:00
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#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_2F8_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_2F8_CLOCK_FREQUENCY
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2017-11-28 06:20:17 +08:00
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2018-11-13 22:15:23 +08:00
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#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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2017-11-28 06:20:17 +08:00
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2018-11-13 22:15:23 +08:00
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#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
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2017-11-09 00:00:37 +08:00
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2018-11-13 22:15:23 +08:00
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#define DT_RAM_SIZE CONFIG_SRAM_SIZE
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2018-05-10 18:22:56 +08:00
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2018-11-13 22:15:23 +08:00
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#define DT_ROM_SIZE CONFIG_FLASH_SIZE
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2018-05-10 18:22:56 +08:00
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2018-11-13 22:15:23 +08:00
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#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
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2018-02-24 00:07:13 +08:00
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/* End of SoC Level DTS fixup file */
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