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zephyr/soc/arm/nxp_imx/Kconfig

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arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
#
# Copyright (c) 2017, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
config SOC_FAMILY_IMX
bool
arm: soc: NXP: Enable SEGGER RTT on all NXP SoCs It seems like SEGGER is supported across all the NXP SoC families so lets enable it across all of them. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-04-27 01:59:58 +08:00
select HAS_SEGGER_RTT
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
# omit prompt to signify a "hidden" option
if SOC_FAMILY_IMX
config SOC_FAMILY
string
default "nxp_imx"
arm: soc: move arm SoCs to top-dir Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-04 04:47:02 +08:00
source "soc/arm/nxp_imx/*/Kconfig.soc"
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
config SOC_PART_NUMBER
string
default SOC_PART_NUMBER_IMX_RT if SOC_SERIES_IMX_RT
arch: Add imx6sx m4 soc support The i.MX 6SoloX SoC is a hybrid multi-core processor composed by one Cortex A9 core and one Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A9 core (running Linux) via RPMsg. The low level drivers come from NXP FreeRTOS BSP and are located at ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README The A9 core is responsible to load the M4 binary application into the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get the M4 out of reset. The A9 can perform these steps at bootloader level after the Linux system has booted. Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-04-18 23:53:39 +08:00
default SOC_PART_NUMBER_IMX_6X_M4 if SOC_SERIES_IMX_6X_M4
default SOC_PART_NUMBER_IMX7_M4 if SOC_SERIES_IMX7_M4
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
help
This string holds the full part number of the SoC. It is a hidden option
that you should not set directly. The part number selection choice defines
the default value for this string.
arch: arm: soc: Cleanup Kconfig inclusion per SoC When we included SoC specific Kconfig files we do something like: gsource "arch/arm/soc/arm/*/Kconfig.soc" However, we should do that inside an if block for that SoC family so as to limit SoC family specific options to only being visible when that SoC family is selected. So we simply move the gsource and related items inside the if SOC_FAMILY_<SOC> block. Fixes: #7452 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-10 23:17:19 +08:00
endif # SOC_FAMILY_IMX