OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/drivers/reset/CMakeLists.txt

15 lines
739 B
CMake
Raw Permalink Normal View History

drivers: added file structure for Reset Controller Driver added needed files for reset controller driver Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
2022-03-22 08:25:39 +08:00
# SPDX-License-Identifier: Apache-2.0
drivers: syscalls: use zephyr_syscall_header This adds a few line use zephyr_syscall_header() to include headers containing syscall function prototypes. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-05-25 06:27:04 +08:00
zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/reset.h)
drivers: added file structure for Reset Controller Driver added needed files for reset controller driver Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
2022-03-22 08:25:39 +08:00
zephyr_library()
drivers: reset: gd32: add initial support Add a new reset driver for GD32 platforms. This driver controls the reset registers from the RCU peripheral. It can be used to restore peripherals to their initial state when initializing a device. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-23 05:41:37 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_GD32 reset_gd32.c)
drivers: reset: added Reset Controller for Raspberry Pi Pico added Reset Controller driver for Raspberry Pi Pico board Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
2022-03-22 08:25:39 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_RPI_PICO reset_rpi_pico.c)
drivers: reset: add Aspeed AST10x0 reset control AST10x0 series SOCs provide the reset controller through the syscon hardware block. The current driver supports the reset line assert, deassert and status for the hardware IPs embedded in the SOC. Each reset line has an ID that can simply map to a bit in syscon registers RESET_CTRL0_ASSERT (group 0) or RESET_CTRL1_ASSERT (group 1). Write bits to RESET_CTRL0_DEASSERT or RESET_CTRL1_DEASSERT will clean the corresponding bits in RESET_CTRL0_ASSERT or RESET_CTRL1_ASSERT registers. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-21 16:56:56 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_AST10X0 reset_ast10x0.c)
drivers: reset: Introduce STM32 reset controller This driver exposes STM32 RCC reset functionality through reset API. Information about RCC register offset and bit is encoded just like GD32. The first 5 least significant bits contains register bit number. Next 12 bits are used to keep RCC register offset. Remaining bits are unused. Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-11-22 22:52:52 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_STM32 reset_stm32.c)
drivers: reset: add support for NuMaker series reset Add Nuvoton numaker series reset controller support. Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-04-10 19:53:23 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_NUMAKER reset_numaker.c)
drivers: reset: Add reset controller for Intel Agilex5 platform This is Intel's proprietary IP which controls individual module reset signals. During each system driver initialization, these reset signals will be used to bring module out of reset state. Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com> Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
2023-07-06 22:35:51 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_INTEL_SOCFPGA reset_intel_socfpga.c)
driver: reset: npcx: add driver support for reset controller Nuvoton NPCX chips have reset registers which allow to reset the peripheral hardware modules. This commit adds the support by implementing the reset driver. Note that only the reset_line_toggle API is supported because of the nature of the reset controller's design. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2024-04-01 10:34:25 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_NPCX reset_npcx.c)
drivers: reset: Add NXP LPC SYSCON reset driver Add driver for the peripheral reset control function of the NXP LPC SYSCON SOC control module. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-05-01 00:08:59 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_NXP_SYSCON reset_lpc_syscon.c)
drivers: reset: Add NXP RSTCTL driver Add driver for NXP RSTCTL reset controller peripheral. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-05-02 01:09:15 +08:00
zephyr_library_sources_ifdef(CONFIG_RESET_NXP_RSTCTL reset_nxp_rstctl.c)