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zephyr/drivers/bbram/CMakeLists.txt

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nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
# Copyright (c) 2021 Google Inc.
# SPDX-License-Identifier: Apache-2.0
zephyr_library()
drivers: bbram: Introduce BBRAM shell Add 'bbram' command which is very convenient tool for examining and modyfying BBRAM content. Examples: Write one byte: $ bbram write backup_regs 0x1 0xaa Write many bytes (starting from 0x13): $ bbram write backup_regs 0x13 0xa 0xb 0xc 0xd 0xe 0xf 0xaa 0xab 0xac Read whole BBRAM: $ bbram read backup_regs Read many bytes (4 bytes starting from address 0x14 in this case): $ bbram read backup_regs 0x14 4 Read one byte (from 0x14 address): $ bbram read backup_regs 0x14 Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-10-25 17:10:32 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_SHELL bbram_shell.c)
bbram: add support from user threads Provide the necessary handlers to support bbram access from userthreads solves #61868. Signed-off-by: Laczen JMS <laczenjms@gmail.com>
2023-08-25 04:05:38 +08:00
zephyr_library_sources_ifdef(CONFIG_USERSPACE bbram_handlers.c)
nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_NPCX bbram_npcx.c)
bbram: npcx: Add emulator Add an emulator for the NPCX BBRAM which supports reading and writing Signed-off-by: Yuval Peress <peress@google.com>
2024-01-06 03:19:08 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_NPCX_EMUL bbram_npcx_emul.c)
zephyr_library_include_directories_ifdef(CONFIG_BBRAM_NPCX .)
drivers: bbram: Add it8xxx2 BBRAM driver implementation Note that the it8xxx2 does not support a status register so that functionality is omitted. This change also adds driver tests that build both the npcx and it8xxx2 drivers. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-08-21 03:31:33 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_IT8XXX2 bbram_it8xxx2.c)
bbram: it8xxx2: Add emulator implementation Add an emulator that supports reading and writing to the it8xxx2 bbram. Signed-off-by: Yuval Peress <peress@google.com>
2024-01-06 03:17:58 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_IT8XXX2_EMUL bbram_it8xxx2_emul.c)
zephyr_library_include_directories_ifdef(CONFIG_BBRAM_IT8XXX2 .)
nuvoton: battery-backed ram Add bindings and entry for the battery-backed ram in the nuvoton npcx. This commit is an upstream port of https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/cros_bbram/nuvoton,npcx-cros-bbram.yaml;l=1;drc=e9af813c36b7b411bf2a01cbc1b09d5fdec49b8a Along with a bit of cleaning up and an emulator. Signed-off-by: Yuval Peress <peress@chromium.org>
2021-01-25 15:51:17 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_EMUL bbram_emul.c)
drivers: bbram: Add Microchip MCP7940N driver Adds Microchip MCP7940N battery-backed RAM support. Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-02-24 20:12:43 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_MICROCHIP_MCP7940N bbram_microchip_mcp7940n.c)
bbram: mcp7940c: Add emulator Add an emulator for the mcp7940c BBRAM that supports reading and writing. Signed-off-by: Yuval Peress <peress@google.com>
2024-01-06 03:18:42 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_MICROCHIP_MCP7940N_EMUL bbram_microchip_mcp7940n_emul.c)
drivers: bbram: Add bbram driver for mec device Add bbram driver for Microchip mec device Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-02-04 03:14:26 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_XEC bbram_xec.c)
drivers: bbram: Introduce STM32 BBRAM driver STM32 battery-backed RAM is organized in 4 byte registers. Number of registers can vary between models from 5 to 32 registers. Usually, the registers are part of RTC. On some variants they are part of tamper module. On STM32F1 the registers are in separate module. For now, only backup registers from RTC are supported. Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-10-24 22:37:21 +08:00
zephyr_library_sources_ifdef(CONFIG_BBRAM_STM32 bbram_stm32.c)