56 lines
1.1 KiB
C
56 lines
1.1 KiB
C
/*
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* Copyright (c) 2020 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
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#include <zephyr/toolchain.h>
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#if CONFIG_CPU_HAS_NXP_MPU
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#include <fsl_sysmpu.h>
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#endif
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void cleanup_arm_nvic(void) {
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/* Allow any pending interrupts to be recognized */
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__ISB();
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__disable_irq();
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/* Disable NVIC interrupts */
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for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
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NVIC->ICER[i] = 0xFFFFFFFF;
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}
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/* Clear pending NVIC interrupts */
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for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
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NVIC->ICPR[i] = 0xFFFFFFFF;
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}
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}
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#if CONFIG_CPU_HAS_ARM_MPU
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__weak void z_arm_clear_arm_mpu_config(void)
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{
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int i;
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int num_regions =
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((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
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for (i = 0; i < num_regions; i++) {
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ARM_MPU_ClrRegion(i);
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}
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}
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#elif CONFIG_CPU_HAS_NXP_MPU
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__weak void z_arm_clear_arm_mpu_config(void)
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{
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int i;
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int num_regions = FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT;
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SYSMPU_Enable(SYSMPU, false);
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/* NXP MPU region 0 is reserved for the debugger */
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for (i = 1; i < num_regions; i++) {
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SYSMPU_RegionEnable(SYSMPU, i, false);
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}
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}
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#endif
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