boot_serial: espressif: ESP32-C3 serial recovery mode
Signed-off-by: Almir Okato <almir.okato@espressif.com>
This commit is contained in:
Almir Okato
Gustavo Henrique Nihei
parent
707a69d40c
commit
09cca3815a
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@ -19,6 +19,7 @@
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#include "bootloader_init.h"
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#include "bootloader_common.h"
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#include "bootloader_console.h"
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#include "bootloader_clock.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_mem.h"
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@ -31,6 +32,10 @@
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#include "soc/efuse_reg.h"
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#include "soc/rtc.h"
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#include "hal/gpio_hal.h"
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#include <hal/gpio_ll.h>
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#include <hal/uart_ll.h>
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#include "esp32c3/rom/cache.h"
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#include "esp32c3/rom/spi_flash.h"
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@ -39,6 +44,12 @@
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extern esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
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#if CONFIG_ESP_CONSOLE_UART_CUSTOM
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static uart_dev_t *alt_console_uart_dev = (CONFIG_ESP_CONSOLE_UART_NUM == 0) ?
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&UART0 :
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&UART1;
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#endif
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void IRAM_ATTR bootloader_configure_spi_pins(int drv)
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{
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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@ -161,15 +172,13 @@ static void bootloader_super_wdt_auto_feed(void)
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
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}
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static void bootloader_init_uart_console(void)
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#if CONFIG_ESP_CONSOLE_UART_CUSTOM
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void IRAM_ATTR esp_rom_uart_putc(char c)
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{
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const int uart_num = 0;
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esp_rom_install_uart_printf();
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esp_rom_uart_tx_wait_idle(0);
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uint32_t clock_hz = UART_CLK_FREQ_ROM;
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esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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while (uart_ll_get_txfifo_len(alt_console_uart_dev) == 0);
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uart_ll_write_txfifo(alt_console_uart_dev, (const uint8_t *) &c, 1);
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}
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#endif
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esp_err_t bootloader_init(void)
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{
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@ -190,7 +199,7 @@ esp_err_t bootloader_init(void)
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// config clock
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bootloader_clock_configure();
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/* initialize uart console, from now on, we can use ets_printf */
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bootloader_init_uart_console();
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bootloader_console_init();
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// update flash ID
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bootloader_flash_update_id();
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// read bootloader header
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@ -12,6 +12,41 @@ CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
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CONFIG_ESP_SCRATCH_OFFSET=0x210000
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CONFIG_ESP_SCRATCH_SIZE=0x40000
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# Enables the MCUboot Serial Recovery, that allows the use of
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# MCUMGR to upload a firmware through the serial port
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# CONFIG_ESP_MCUBOOT_SERIAL=y
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# Use Serial through USB JTAG Serial port for Serial Recovery
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# CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG=y
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# Use sector erasing (recommended) instead of entire image size
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# erasing when uploading through Serial Recovery
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# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
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# GPIO used to boot on Serial Recovery
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# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=5
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# GPIO input type (0 for Pull-down, 1 for Pull-up)
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# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
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# GPIO signal value
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# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
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# Delay time for identify the GPIO signal
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# CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
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# UART port used for serial communication (not needed when using USB)
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# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
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# GPIO for Serial RX signal
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# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=8
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# GPIO for Serial TX signal
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# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=9
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# Use UART0 for console printing (use either UART or USB alone)
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CONFIG_ESP_CONSOLE_UART=y
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CONFIG_ESP_CONSOLE_UART_NUM=0
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# Configures alternative UART port for console printing
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# (UART_NUM=0 must not be changed)
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# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
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# CONFIG_ESP_CONSOLE_UART_TX_GPIO=9
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# CONFIG_ESP_CONSOLE_UART_RX_GPIO=8
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# Use USB JTAG Serial for console printing
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# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
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# CONFIG_ESP_SIGN_EC256=y
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# CONFIG_ESP_SIGN_ED25519=n
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# CONFIG_ESP_SIGN_RSA=n
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@ -33,13 +33,13 @@ SECTIONS
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*libhal.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_init_common.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_flash.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_random.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
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*libhal.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
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*libhal.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_utility.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_sha.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_console.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_panic.*(.literal .text .literal.* .text.*)
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*libhal.a:bootloader_soc.*(.literal .text .literal.* .text.*)
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@ -0,0 +1,226 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <bootutil/bootutil_log.h>
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#include <esp_rom_uart.h>
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#include <esp_rom_gpio.h>
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#include <esp_rom_sys.h>
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#include <esp_rom_caps.h>
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#include <soc/uart_periph.h>
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#include <soc/gpio_struct.h>
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#include <soc/io_mux_reg.h>
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#include <soc/rtc.h>
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#include <hal/gpio_types.h>
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#include <hal/gpio_ll.h>
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#include <hal/uart_ll.h>
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#include <hal/clk_gate_ll.h>
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#include <hal/usb_serial_jtag_ll.h>
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#include <hal/gpio_hal.h>
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#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
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#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
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#else
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#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_5
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#endif
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#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
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#define SERIAL_BOOT_GPIO_DETECT_VAL CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
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#else
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#define SERIAL_BOOT_GPIO_DETECT_VAL 1
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#endif
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#ifdef CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
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#define SERIAL_BOOT_DETECT_DELAY_S CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
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#else
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#define SERIAL_BOOT_DETECT_DELAY_S 5
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#endif
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#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
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#define SERIAL_BOOT_GPIO_INPUT_TYPE CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
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#else
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// pull-down
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#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
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#endif
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#ifndef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
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#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
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#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
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#else
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#define SERIAL_BOOT_UART_NUM ESP_ROM_UART_1
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#endif
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#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
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#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
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#else
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#define SERIAL_BOOT_GPIO_RX GPIO_NUM_8
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#endif
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#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
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#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
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#else
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#define SERIAL_BOOT_GPIO_TX GPIO_NUM_9
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#endif
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static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
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&UART0 :
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&UART1;
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#endif
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void console_write(const char *str, int cnt)
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{
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#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
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usb_serial_jtag_ll_txfifo_flush();
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while (!usb_serial_jtag_ll_txfifo_writable()) {
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MCUBOOT_WATCHDOG_FEED();
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}
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usb_serial_jtag_ll_write_txfifo((const uint8_t *)str, cnt);
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usb_serial_jtag_ll_txfifo_flush();
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#else
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uint32_t tx_len;
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uint32_t write_len;
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do {
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tx_len = uart_ll_get_txfifo_len(serial_boot_uart_dev);
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if (tx_len > 0) {
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write_len = tx_len < cnt ? tx_len : cnt;
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uart_ll_write_txfifo(serial_boot_uart_dev, (const uint8_t *)str, write_len);
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cnt -= write_len;
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}
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MCUBOOT_WATCHDOG_FEED();
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esp_rom_delay_us(1000);
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} while (cnt > 0);
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#endif
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}
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int console_read(char *str, int cnt, int *newline)
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{
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#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
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uint32_t read_len = 0;
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esp_rom_delay_us(1000);
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do {
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if (usb_serial_jtag_ll_rxfifo_data_available()) {
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usb_serial_jtag_ll_read_rxfifo((uint8_t *)&str[read_len], 1);
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read_len++;
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}
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MCUBOOT_WATCHDOG_FEED();
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esp_rom_delay_us(1000);
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} while (!(read_len == cnt || str[read_len - 1] == '\n'));
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*newline = (str[read_len - 1] == '\n') ? 1 : 0;
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return read_len;
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#else
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uint32_t len = 0;
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uint32_t read_len = 0;
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bool stop = false;
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do {
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len = uart_ll_get_rxfifo_len(serial_boot_uart_dev);
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if (len > 0) {
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for (uint32_t i = 0; i < len; i++) {
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/* Read the character from the RX FIFO */
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uart_ll_read_rxfifo(serial_boot_uart_dev, (uint8_t *)&str[read_len], 1);
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read_len++;
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if (read_len == cnt - 1|| str[read_len - 1] == '\n') {
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stop = true;
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break;
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}
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}
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}
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MCUBOOT_WATCHDOG_FEED();
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esp_rom_delay_us(1000);
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} while (!stop);
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*newline = (str[read_len - 1] == '\n') ? 1 : 0;
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return read_len;
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#endif
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}
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int boot_console_init(void)
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{
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BOOT_LOG_INF("Initializing serial boot pins");
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#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
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usb_serial_jtag_ll_txfifo_flush();
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esp_rom_uart_tx_wait_idle(0);
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#else
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/* Enable GPIO for UART RX */
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esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
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esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
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UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_RX_PIN_IDX),
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0);
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gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_RX);
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esp_rom_gpio_pad_pullup_only(SERIAL_BOOT_GPIO_RX);
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/* Enable GPIO for UART TX */
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esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_TX);
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esp_rom_gpio_connect_out_signal(SERIAL_BOOT_GPIO_TX,
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UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_TX_PIN_IDX),
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0, 0);
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gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
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uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_APB);
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uart_ll_set_mode_normal(serial_boot_uart_dev);
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uart_ll_set_baudrate(serial_boot_uart_dev, 115200);
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uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
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uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
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uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
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uart_ll_set_data_bit_num(serial_boot_uart_dev, UART_DATA_8_BITS);
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uart_ll_set_tx_idle_num(serial_boot_uart_dev, 0);
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uart_ll_set_hw_flow_ctrl(serial_boot_uart_dev, UART_HW_FLOWCTRL_DISABLE, 100);
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periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + SERIAL_BOOT_UART_NUM);
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uart_ll_txfifo_rst(serial_boot_uart_dev);
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uart_ll_rxfifo_rst(serial_boot_uart_dev);
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esp_rom_delay_us(50000);
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#endif
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return 0;
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}
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bool boot_serial_detect_pin(void)
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{
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bool detected = false;
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int pin_value = 0;
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esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_DETECT);
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gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_DETECT);
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switch (SERIAL_BOOT_GPIO_INPUT_TYPE) {
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// Pull-down
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case 0:
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gpio_ll_pulldown_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
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break;
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// Pull-up
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case 1:
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gpio_ll_pullup_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
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break;
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}
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esp_rom_delay_us(50000);
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pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
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detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
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esp_rom_delay_us(50000);
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if (detected) {
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if (SERIAL_BOOT_DETECT_DELAY_S > 0) {
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/* The delay time is an approximation */
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for (int i = 0; i < (SERIAL_BOOT_DETECT_DELAY_S * 100); i++) {
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esp_rom_delay_us(10000);
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pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
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detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
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if (!detected) {
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break;
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}
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}
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}
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}
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return detected;
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}
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@ -552,7 +552,7 @@ Serial recovery mode allows management through MCUMGR (more information and how
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---
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***Note***
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Supported on ESP32.
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Supported on ESP32 and ESP32-C3.
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---
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@ -581,6 +581,28 @@ When enabled, the bootloader checks the if the GPIO `<CONFIG_ESP_SERIAL_BOOT_GPI
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Serial mode then uses the UART port configured for communication (`<CONFIG_ESP_SERIAL_BOOT_UART_NUM>`, pins `<CONFIG_ESP_SERIAL_BOOT_GPIO_RX>`, `<CONFIG_ESP_SERIAL_BOOT_GPIO_RX>`).
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### [Serial Recovery through USB JTAG Serial port](#serial-recovery-through-usb-jtag-serial-port)
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Some chips, like ESP32-C3, have an integrated USB JTAG Serial Controller that implements a serial port (CDC) that can also be used for handling MCUboot Serial Recovery.
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More information about the USB pins and hardware configuration on ESP32-C3: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/api-guides/usb-serial-jtag-console.html.
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Configuration example:
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```
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# Use Serial through USB JTAG Serial port for Serial Recovery
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CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG=y
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# Use sector erasing (recommended) instead of entire image size
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# erasing when uploading through Serial Recovery
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CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
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# GPIO used to boot on Serial Recovery
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CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=5
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# GPIO input type (0 for Pull-down, 1 for Pull-up)
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CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
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# GPIO signal value
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CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
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# Delay time for identify the GPIO signal
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CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
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```
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### [MCUMGR image upload example](#mcumgr-image-upload-example)
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After entering the Serial recovery mode on the device, MCUMGR can be used as following:
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