90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
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/*******************************************************************************
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* File Name: cycfg_pins.c
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*
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* Description:
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* Pin configuration
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* This file was automatically generated and should not be modified.
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* Device Configurator: 2.0.0.1483
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* Device Support Library (../../../psoc6pdl): 1.3.1.1499
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_pins.h"
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const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config =
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{
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.outVal = 1,
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.driveMode = CY_GPIO_DM_HIGHZ,
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.hsiom = CYBSP_UART_RX_HSIOM,
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.intEdge = CY_GPIO_INTR_DISABLE,
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.intMask = 0UL,
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.vtrip = CY_GPIO_VTRIP_CMOS,
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.slewRate = CY_GPIO_SLEW_FAST,
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.driveSel = CY_GPIO_DRIVE_1_2,
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.vregEn = 0UL,
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.ibufMode = 0UL,
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.vtripSel = 0UL,
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.vrefSel = 0UL,
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.vohSel = 0UL,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_UART_RX_obj =
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{
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.type = CYHAL_RSC_GPIO,
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.block_num = CYBSP_UART_RX_PORT_NUM,
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.channel_num = CYBSP_UART_RX_PIN,
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};
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#endif //defined (CY_USING_HAL)
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const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config =
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{
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.outVal = 1,
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.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
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.hsiom = CYBSP_UART_TX_HSIOM,
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.intEdge = CY_GPIO_INTR_DISABLE,
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.intMask = 0UL,
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.vtrip = CY_GPIO_VTRIP_CMOS,
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.slewRate = CY_GPIO_SLEW_FAST,
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.driveSel = CY_GPIO_DRIVE_1_2,
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.vregEn = 0UL,
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.ibufMode = 0UL,
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.vtripSel = 0UL,
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.vrefSel = 0UL,
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.vohSel = 0UL,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_UART_TX_obj =
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{
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.type = CYHAL_RSC_GPIO,
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.block_num = CYBSP_UART_TX_PORT_NUM,
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.channel_num = CYBSP_UART_TX_PIN,
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};
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#endif //defined (CY_USING_HAL)
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void init_cycfg_pins(void)
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{
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Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_UART_RX_obj);
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#endif //defined (CY_USING_HAL)
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Cy_GPIO_Pin_Init(CYBSP_UART_TX_PORT, CYBSP_UART_TX_PIN, &CYBSP_UART_TX_config);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_UART_TX_obj);
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#endif //defined (CY_USING_HAL)
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}
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